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I'm using the DE2 board and can successfully write and read back audio samples from the SDRAM. I can now control the location of the read pointer for delays etc- basic stuff for you lot but pretty fun for me :)
What i'm trying to do now is create multiple read pointers i.e taps at so many samples (or memory locations) apart. I've spent a lot of time trying out different ideas to get this to work but i've run out of ideas now and i need a bit of help. The SDRAM is instantiated in SOPC builder and i've created a memory mapped master component to interface my VHDL read/writes etc. Is this even possible with what i've got and the way i'm implementing the sdram?Link Copied
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You will have to read all your memory locations sequentially. You can either do that in your own code, using a counter or a state machine for example, or create multiple masters and let the SOPC builder arbitrater logic do the work for you.
The best choice depends on the kind of accesses you want to do. They both add complexity in different areas.- Mark as New
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Cheers for the reply
I've added another state (write2_state) to the ram state machine and this appears to be working. Surely there's gonna be a limit here as to how may taps i can have? Is it ever possible to read all these taps out in a parallel fashion for a circular buffer implementation.- Mark as New
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As Daixiwen explained, the SDRAM accesses have to be sequential by nature. The SOPC interface adds some overhead to it, so for maximum throughput respectively number of taps, a pure HDL design would be reasonabble. I'm however under the impression, that a SOPC based access will allow many taps for usual audio sampling rates, e.g. 44 kHz.
You can write a simple test program to determine the available interface speed.- Mark as New
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FvM i'd be very interested in this simple test program to determine speed and therefor allowing me to see how many more taps i can get out of the SDRAM within 1 audio sample.
Where do i start?
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