Problem with GPIO assignments for the DE2

[Altera_Forum]

I have a feeling this might be some kind of bug? I'm running Quartus 11.0. 

 I am using the GPIO_0 for various inputs and outputs and connecting my VHDL entities to the GPIO pins on a top level BDF.   The problem is that, it seems i cannot have an input and an ouput on the same GPIO at the same time! It works for just inputs alone or just outputs alone but not together.   It seems to be a problem with pin assignments. The pin planner misses out the square brackets. See the screenshots...  Ok so here are inputs only which works fine- pins are assigned http://www.flickr.com/photos/61859309@n07/6836878606/  Now, i add just one output pin and all the GPIO assignments mess up and Quartus misses the square brackets! http://www.flickr.com/photos/61859309@n07/6836869314/

[Altera_Forum]

How does the RTL look: 

 Bidirectional pins need to be defined in the RTL for the pin-planner to connect them properly.  IE:  for verilog they would be defined some like:  ...  inout [15:0] GPIO_0,  ...  assign GPIO_0 = OE_logic_c ? GPIO_r : 'bz; // Tristates the outputs, sets direction as input  ...

[Altera_Forum]

These arent bidirectional pins.  

 I basically had to modify the pin assignments and take out the [] square brackets. All works now.  Cheers for the help anyway