I am currently experiencing a problem with an Arria 10 FPGA (10AS066K3F40E2SG) design that fails to fit with Quartus Prime Pro 18.1.
During the Place Stage, Quartus posts several info messages (19797+19727), warning messages (19726) and error messages (19724) about difficulties then failures to fit.
- Warning(19726): Fitter is having difficulty packing for clock region in locations from lower-left (<number>, <number>) to upper-right (<number>, <number>), as it requires <number> LABs but only <number> LABs are available exclusively for that region
- Info(19797): The following node of the above-mentioned region failed to pack: <node name>
- Info(19727): Fitter will now perform the packing at the highest effort level
- Error(19724): Fitter requires <number> LABs for region created by intersection of clock and clock regions in locations from lower-left (<number>, <number>) to upper-right (<number>, <number>), but only <number> LABs are available exclusively for that region
The online help about Error(19724) suggests:
- CAUSE: Legal clustering cannot be found in a region. It could be a clock region, a Logic Lock region, or an intersection of both.
- ACTION: Please increase the size of any Logic Lock region or the clock region in the corresponding locations.
However, I do not really understand how I can increase the size of a clock region.
If I consider the message sequence, it seems the concerned clocks are recovered clocks outputted by the Arria 10 transceiver RX channels. Please note I have not manually specified any Logic Lock region nor any clock region in the project assignments.
May you please support me to understand this issue and to solve it ?
I also have the same problem with Cyclone 10 GX. Problem is only solved when manual logic placement asignments are used (which are supplied with the DP RX-TX 4K Reference Design). The interesting part is manual logic placement works even if the region is not adjacent to transceiver block. Also problem is not related with the device size because the logic utilization is around %50. I am looking for a systematic approach for this issue.
This error implies some clock regions might have been made too small during the compilation. There is option to counteract this issue, in your .qsf file, try compiling with the following assignment:
set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION"
Alternatively, to enlarge the clock region, in your .qsf file, you can use Clock Region assignments.
set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity
.https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl-pro-qsf-referenc... (p400) (CLOCK_REGION Setting reference)
" set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION" " didn't help to eliminate error I encountered but "set_instance_assignment -name CLOCK_REGION ..." worked perfectly well. Thanks a lot for your help.
Hi Huseyin, hi Syafieq,
Thanks to both of you for your kind responses.
Unfortunately, I confirm that" set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION" " did not help.
Like Huseyin, I can say that my problem was not related with the device size, because the logic utilization was around 30%.
I temporarily addessed this issue by reducing the hardware footprint of my design, specifically targeting the fanout of the concerned clocks. That is why I have not exprerimented the second suggestion very quickly.
With the complete design, I finally managed to fit without errors by promoting the concerned clocks to large periphery clocks : "set_instance_assignment -name GLOBAL_SIGNAL LARGE_PERIPHERY_CLOCK -to <clock_signal_name>".
I suppose it has the same kind of impact as your suggestion of enlarging clock regions with the CLOCK_REGION assignment.