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Altera_Forum
Honored Contributor I
813 Views

Please help with PLL

Hello! 

I'm trying to use PLL to increase frequency of my system. I use Quartus 17 and de0-nano-SoC board.  

Steps I did: 

1. On my IP catalog I chose Altera PLL: https://screencast.com/t/nshqodhrq 

2. Set settings as the following: https://screencast.com/t/vphamvpt (I have tried to set "Enable locked output port" and "Enable physical output clock parameters" doesn't help) 

3. Once qip/sip is generated and added to the library on my top module I do : 

module top_module ( input clk ); reg clk_pll; reg pll_reset = 0; newpll testpll (.refclk(clk), .rst(pll_reset), .outclk_0(clk_pll)); ....  

 

But the system doesn't work, modules don't receive signals by clk_pll 

 

Please, any suggestions
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3 Replies
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Hello! 

I'm trying to use PLL to increase frequency of my system. I use Quartus 17 and de0-nano-SoC board.  

Steps I did: 

1. On my IP catalog I chose Altera PLL: https://screencast.com/t/nshqodhrq 

2. Set settings as the following: https://screencast.com/t/vphamvpt (I have tried to set "Enable locked output port" and "Enable physical output clock parameters" doesn't help) 

3. Once qip/sip is generated and added to the library on my top module I do : 

module top_module ( input clk ); reg clk_pll; reg pll_reset = 0; newpll testpll (.refclk(clk), .rst(pll_reset), .outclk_0(clk_pll)); ....  

 

But the system doesn't work, modules don't receive signals by clk_pll 

 

Please, any suggestions 

--- Quote End ---  

 

 

Have you got ref clk driven
Altera_Forum
Honored Contributor I
53 Views

Yes, it works fine, when I use just clk (it comes from V11, https://screencast.com/t/bdsshstrk

Is it true that pll_reset is not necessary to start pll?
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Yes, it works fine, when I use just clk (it comes from V11, https://screencast.com/t/bdsshstrk

Is it true that pll_reset is not necessary to start pll? 

--- Quote End ---  

 

 

You better double check naming and mapping as I see some differences between your naming above and those in your pll link 

reset is optional so you can keep it released for now but also add pll lock output to see if it works.
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