I have a soft NIOS II processor instantiated on an Altera FPGA. I have 4 JTAG pins connected from the FPGA to a FTDI chip (lets call them A1, A2, A3, A4). I have the JTAG pins from 2 MCUs connected to the FPGA also (lets call them B1, B2, B3, B4 and C1, C2, C3, C4).In software running on the NIOS I want to be able to select which two sets of pins I want to connect (i.e. A to B or A to C). You have to do pins assignments in verilog though. Is there a way to call a block of verilog code from a c program running on the NIOS?
FPGA JTAG pins are dedicated resources with fixed location and can't be selected by configuration or user logic.FPGA logic blocks aren't "called", neither from other FPGA modules nor a soft processor. The logic operation can be however made conditional, depending on a register written by the soft processor.