Power schematic for Cyclone IV

[Altera_Forum]

Hi, i am designing a very simple development board and need some tips on Cyclone IV power design. The board will be used for learning purposes with simpled designes. It is not aimed for very fast deisgns (100Mhz max i would say). The 3.3V, 2.5V and 1.2V are generated with standard 1117 LDOs with a bypassing 22uF tantalum capacitor. For decoupling i am using a 100nF x7R capacitor at each pin. My doubt is on the VCAA and VCCD desing. 

 Is the following schematic a reasonable circuit? The 1.2V is used fo VCCINT. The filter is a ferrite bead, i still have to chose the 100Mhz impedance. I added the 4.7uF X5R capacitor but still not sure if is really needed... the 2 100nF capacitors at VCAA adn VCCD are the decoupling capacitors at the pins.  https://www.alteraforum.com/forum/attachment.php?attachmentid=6785   Any sugestion is more than appreciated. The board is just for very low level (and low cost) FPGA design and learning.  Regards,  LR

[Altera_Forum]

This design looks good to me. 

 If you want to simulate your filter, then Linear Technology LTspice is a nice tool.  TDK have SPICE models for their capacitors and ferrite beads on their web site.  Ferrite bead + capacitor PI filters can have peaking in their response. The peaking can be damped with a series resistor, but then that resistor causes a voltage drop, so is not appropriate for high-current supplies.  Cheers, Dave

[Altera_Forum]

Hello, Dave! 

Your answers regarding the usage of 1117 LDOs to power Cyclone IV seem to be controversial: ----------------------------------------------------------------------------------   --- Quote Start ---   The 3.3v, 2.5v and 1.2v are generated with standard 1117 ldos with a bypassing 22uF tantalum capacitor.   --- Quote End ---     --- Quote Start ---  this design looks good to me.  --- Quote End ---   ----------------------------------------------------------------------------------   --- Quote Start ---  Why Power Supply on "Cyclone IV GX FPGA Development Kit" is so sophisticated? why not use simple 3-pin ldo instead of multi-pin Linear Regulators used on this Kit?   --- Quote End ---     --- Quote Start ---   FPGAs have a power-on requirement that the power rails ramp in a well-defined time period. Multi-pin linear regulators generally have enable and soft-start functions that can be used to aid in power-on sequencing. a simple 3-pin linear regulator does not provide this functionality.   --- Quote End ---   ----------------------------------------------------------------------------------

[Altera_Forum]

--- Quote Start ---   Your answers regarding the usage of 1117 LDOs to power Cyclone IV seem to be controversial:   --- Quote End ---    I don't recall any controversy :)  Most people just drop linear regulators onto a board and hope-for-the-best.   I design my power supplies very carefully, simulate them, perform transient response tests, use a frequency response analyzer to measure their gain, and use a programmable load tester to measure efficiency.  Based on that, who would you take advice from?  http://www.ovro.caltech.edu/~dwh/wbsddc/power_supply_design.pdf http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf  Cheers, Dave