Power-up sequence question about Cyclone 10 GX

[MinzhiWang]

Hi,

I'm reading an692, which makes 3 groups for Cyclone 10 GX voltage rails, as following table 3.

I also find one note for this power-up sequence:

I have question for above "note". What's the meaning of "driving of unpowered GPIO or transceiver pins"? Or what's unpowered GPIO? Can anyone give a instance of this "driving unpowered GPIO" situation?

In an692, following table 3, there is other comments for group 2 and group 3 combining. I found the example of group 2&3 combining from C10GX pin connection guidelines. Comparing with table 3, the following example re-groups voltage rails. Can I combine following group 1&2, then only two groups required? For following groups 1&2 belongs to table 3's group 1.

Thanks

Best Regard

[FvM]

Hi,
"driving unpowered GPIO" means driving pins externally that have not yet their respective VCCIO ramped up, causing forward biasing of clamp diodes and possible violation of maximal input current. The condition should be checked for all FPGA IO pins.

[MinzhiWang]

Hi FvM,

I'm just very inteasted on this "driving unpowered GPIO". As you said, this means driving pins externally that have not yet their repective VCCIO ramped up. But how  can this happen? Can you help clarify this situation?

I just wonder how/what cause that "note" situation happenning. 

Thanks

[Fakhrul · Accepted solution]

Hi MinzhiWang,

Driving unpowered GPIO or transceiver pins can happen if external signals are applied before the FPGA's VCCIO or transceiver power rails are fully powered. The "driving unpowered GPIO" situation typically arises in scenarios where external devices drive signals into the FPGA before the FPGA's associated VCCIO (voltage supply for I/O banks) is powered up. To avoid this, ensure proper power sequencing, where VCCIO or transceiver rails are stable before external signals are active - If the FPGA's power supply is not properly sequenced, external devices might start operating and drive signals into the FPGA I/O pins while the FPGA's VCCIO is still ramping up or unpowered..

You can only combine and ramp up Group 3 power rails with Group 2 if both share the same voltage level and regulator as Group 2’s VCCPT.

Regards,

Fakhrul

[Fakhrul]

Hi MinzhiWang,

I noticed you marked my earlier comment as the solution. I'm glad your question has been addressed!

At this point, I’ll transition this thread to community support. If you have any new questions, feel free to open a new thread to receive assistance from Intel experts. Otherwise, the community members will continue to help you here.

Thank you for your engagement!

Best regards,

Fakhrul