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Altera_Forum
Honored Contributor I
1,052 Views

Problem in Inter FPGA Transfer

hi,  

I am having a customized board with 2 Stratix V FPGA on it. i wanted to transfer the data from one FPGA to another directly ( Pin to Pin ) without ant protocol. The clock rate is 10 Mhz .  

I am finding that the data received is not same as what i had sent. The problem is in the SDC file in which i had given the INPUT_DELAY and OUTPUT_DELAY commands.  

Kindly suggest me how to find the accurate delays to be given in SDC file and what other commands i should enter to get the correct data . 

 

 

Saurabh
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4 Replies
Altera_Forum
Honored Contributor I
22 Views

 

--- Quote Start ---  

hi,  

I am having a customized board with 2 Stratix V FPGA on it. i wanted to transfer the data from one FPGA to another directly ( Pin to Pin ) without ant protocol. The clock rate is 10 Mhz .  

I am finding that the data received is not same as what i had sent. The problem is in the SDC file in which i had given the INPUT_DELAY and OUTPUT_DELAY commands.  

Kindly suggest me how to find the accurate delays to be given in SDC file and what other commands i should enter to get the correct data . 

 

Saurabh 

--- Quote End ---  

 

 

You need to describe the protocol you are using in more detail. Is it a single data line, as in a serial UART but at 10MHz baud rate? Or is it embedded clock/data as would be in NRZ/NRZI encoded? Or do you have a separate clock line and data line? Or ... ? 

 

It sounds like you have more than one signal (like clock + data), as the data input/output delay on a single line would not be an issue.
Altera_Forum
Honored Contributor I
22 Views

Hi, 

 

If you just send data + clock, you can just invert the clock on the reception part to sample the data in the eye of the signal.  

The input_delay / output_delay commands will probably be useless at 10MHz.
Altera_Forum
Honored Contributor I
22 Views

 

--- Quote Start ---  

Hi, 

 

If you just send data + clock, you can just invert the clock on the reception part to sample the data in the eye of the signal.  

The input_delay / output_delay commands will probably be useless at 10MHz. 

--- Quote End ---  

 

 

 

 

thanks.....
Altera_Forum
Honored Contributor I
22 Views

If you are essentially creating a source synchronous interface between the two devices, check out this training and the app note referenced within (don't remember which one it is offhand): 

 

https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=syn...