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Altera_Forum
Honored Contributor I
836 Views

Problem to include ALTASMI_PARALLEL to Cyclone III project.

I'm trying to include ALTASMI_PARALLEL in Cyclone III project. 

Mega Wizard generated the following code 

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY EPCS_CONT IS PORT ( addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); clkin : IN STD_LOGIC ; datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rden : IN STD_LOGIC ; read : IN STD_LOGIC ; write : IN STD_LOGIC ; busy : OUT STD_LOGIC ; data_valid : OUT STD_LOGIC ; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); illegal_write : OUT STD_LOGIC ); END EPCS_CONT; ARCHITECTURE SYN OF epcs_cont IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altasmi_parallel GENERIC ( data_width : STRING; epcs_type : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; page_size : NATURAL; port_bulk_erase : STRING; port_fast_read : STRING; port_illegal_erase : STRING; port_illegal_write : STRING; port_rdid_out : STRING; port_read_address : STRING; port_read_rdid : STRING; port_read_sid : STRING; port_read_status : STRING; port_sector_erase : STRING; port_sector_protect : STRING; port_shift_bytes : STRING; port_wren : STRING; port_write : STRING; use_eab : STRING ); PORT ( illegal_write : OUT STD_LOGIC ; read : IN STD_LOGIC ; addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); busy : OUT STD_LOGIC ; clkin : IN STD_LOGIC ; data_valid : OUT STD_LOGIC ; datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rden : IN STD_LOGIC ; write : IN STD_LOGIC ; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN illegal_write <= sub_wire0; busy <= sub_wire1; data_valid <= sub_wire2; dataout <= sub_wire3(7 DOWNTO 0); ALTASMI_PARALLEL_component : ALTASMI_PARALLEL GENERIC MAP ( data_width => "STANDARD", epcs_type => "EPCS16", intended_device_family => "Cyclone III", lpm_hint => "UNUSED", lpm_type => "altasmi_parallel", page_size => 256, port_bulk_erase => "PORT_UNUSED", port_fast_read => "PORT_UNUSED", port_illegal_erase => "PORT_UNUSED", port_illegal_write => "PORT_USED", port_rdid_out => "PORT_UNUSED", port_read_address => "PORT_UNUSED", port_read_rdid => "PORT_UNUSED", port_read_sid => "PORT_UNUSED", port_read_status => "PORT_UNUSED", port_sector_erase => "PORT_UNUSED", port_sector_protect => "PORT_UNUSED", port_shift_bytes => "PORT_UNUSED", port_wren => "PORT_UNUSED", port_write => "PORT_USED", use_eab => "ON" ) PORT MAP ( read => read, addr => addr, clkin => clkin, datain => datain, rden => rden, write => write, illegal_write => sub_wire0, busy => sub_wire1, data_valid => sub_wire2, dataout => sub_wire3 ); END SYN;  

I include it in TOP  

component EPCS_CONT is port ( addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); clkin : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rden : IN STD_LOGIC; read : IN STD_LOGIC; shift_bytes : IN STD_LOGIC; write : IN STD_LOGIC; busy : OUT STD_LOGIC; data_valid : OUT STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); illegal_write : OUT STD_LOGIC ); end component; signal addr_sig : STD_LOGIC_VECTOR (23 DOWNTO 0); signal datain_sig : STD_LOGIC_VECTOR (7 DOWNTO 0); signal rden_sig : STD_LOGIC; signal read_sig : STD_LOGIC; signal shift_bytes_sig : STD_LOGIC; signal write_sig : STD_LOGIC; signal busy_sig : STD_LOGIC; signal data_valid_sig : STD_LOGIC; signal dataout_sig : STD_LOGIC_VECTOR (7 DOWNTO 0); signal illegal_write_sig : STD_LOGIC; U_EPCS_CONT : EPCS_CONT port map ( addr => addr_sig, clkin => CLK_30MHZ, datain => datain_sig, rden => rden_sig, read => read_sig, shift_bytes => shift_bytes_sig, write => write_sig, busy => busy_sig, data_valid => data_valid_sig, dataout => dataout_sig, illegal_write => illegal_write_sig );  

While compiling get error - Error (12152): Can't elaborate user hierarchy "EPCS_CONT:U_EPCS_CONT|altasmi_parallel:ALTASMI_PARALLEL_component" 

What's the problem?
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
45 Views

shift_bytes input is not present in your component entity but present in your component instanciation

Altera_Forum
Honored Contributor I
45 Views

 

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shift_bytes input is not present in your component entity but present in your component instanciation 

--- Quote End ---  

 

I removed the shift_bytes input - still the same problem.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

Can't elaborate user hierarchy "EPCS_CONT:U_EPCS_CONT|altasmi_parallel:ALTASMI_PARALLEL_component" 

--- Quote End ---  

 

There are detailed error messages above this line. Look for the first red line in the compilation report or click the "Show error messages" filter. 

 

 

--- Quote Start ---  

Error (272006): shift_bytes input port must be used in combination with page write circuit 

Error (287078): Assertion error: Valid clear box generator not found or Errors encountered during clear box generation 

Error (12152): Can't elaborate user hierarchy "altasmi_parallel:ALTASMI_PARALLEL_component" 

 

--- Quote End ---  

 

 

You are obviously ignoring some requirements for the component, review the manual thoroughly.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

There are detailed error messages above this line. Look for the first red line in the compilation report or click the "Show error messages" filter. 

 

 

You are obviously ignoring some requirements for the component, review the manual thoroughly. 

--- Quote End ---  

 

You are right. But I don't know how to deal with the errors. 

 

What should I do wit this? 

ASSERT (CBXI_PARAMETER != "NOTHING") 

REPORT "Valid clear box generator not found or Errors encountered during clear box generation" 

 

Oh, I found the problem - it should be page_size => 1, in Single byte write mode.  

What mode is better to use - Single byte write or Page write?
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