Problem with PLL in EP1C12 device

[Altera_Forum]

Hello everyone, long time no see =] 

 Recently I've built my own evaluation board with EP1C12 Cyclone device (yes, it's an old one, but I obtained it for free). The board is working, I can configure the FPGA using JTAG Byte Blaster (parallel port), also FPGA chip is working properly, except the PLL. I've created simple test project, which uses PLL. The PLL is created as a Altera Megafunction and it's suppose to double the clock frequency (from 50 MHz to 100 MHz). Reset and clock signals are connected properly to PLL core. What could be wrong ? The code is listed below.  PLL_test.vhd:  library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity PLL_test is generic ( DIV_FACTOR : positive := 20 ); port ( clk : in std_logic; nrst : in std_logic; divout : out std_logic; locked : out std_logic ); end PLL_test; architecture behavioral of PLL_test is COMPONENT PLL IS PORT ( areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END COMPONENT; signal divider : std_logic_vector(15 downto 0); signal div_rst,div_clk,PLL_lock : std_logic; begin clk_mul : PLL PORT MAP ( areset => not nrst, inclk0 => clk, c0 => div_clk, locked => PLL_lock ); div_rst <= PLL_lock and nrst; locked <= PLL_lock; freq_divider : process(div_clk,div_rst) is begin if div_rst = '0' then divider <= (others => '0'); divout <= '0'; elsif rising_edge(div_clk) then divider <= divider + 1; if divider <= DIV_FACTOR/2 then divout <= '0'; else divout <= '1'; end if; if divider = DIV_FACTOR then divider <= (others => '0'); end if; end if; end process freq_divider; end behavioral;  The divider is supposed to generate signal with frequency ten times lower than PLL clock out frequency (10 MHz in this case), cause my oscilloscope is old and has bandwidth of 25 MHz.

[Altera_Forum]

I can't see, if the PLL Megafunction is configured correctly, but the clock divider is hold in reset by this line, so no output can be expected. 

div_rst <= PLL_lock and nrst; P.S.: O.K., I see it's actually ndiv_rst, it should work then. The division factor is 21 in your design, resulting in 4.76 MHz output clock with 100 MHz input. Do you see a locked state?

[Altera_Forum]

The div_rst signal is active low. When the nrst signal is off (high) and PLL_lock signal is on (high) then div_rst is off (high), so no reset occurs. It's simple precaution against unexpected behavior of PLL before it's locked.

[Altera_Forum]

I am not sure about your testing of std_logic against integer. 

 if divider <= DIV_FACTOR/2 ?? if divider = DIV_FACTOR ??

[Altera_Forum]

The IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED libraries make it possible ;) I forgot to mention that in timing simulation everything is OK.

[Altera_Forum]

--- Quote Start ---  I forgot to mention that in timing simulation everything is OK.  --- Quote End ---  So it should work in hardware as well. Are you sure to have assigned the pins correctly? You didn't mention a particular problem that you experienced with your design.

[Altera_Forum]

I've checked pin connections several times. I've checked if any of used pins isn't broken. Everything is OK, except the PLL won't start. The lock signal is constantly low.

[Altera_Forum]

Make sure your clk is indeed 50Mhz to fpga

[Altera_Forum]

OK, but as a clock source is quartz generator, like this (but 50 MHz): http://www.tme.eu/generator-kwarcowy-obudowa-metalowa-50mhz-33v/arts/pl/a09/qo1_00.html , so it's almost impossible that the input frequency is different.

[Altera_Forum]

You better probe it and measure or use it inside fpga bypassing PLL and see it is toggling at least.

[Altera_Forum]

I used this clock directly and FPGA works properly, the output is toggling.

[Altera_Forum]

I don't see anything wrong with your code.  

I know once a stratix PLL didn't lock because of long reset. Try these:   remove reset signal check the lock signal directly.

[Altera_Forum]

I tried Your solution, but it still doesn't work. I even tried to use other PLL. No luck there either. Any ideas ?

[Altera_Forum]

In my opinion, possible causes are: 

- Wrong clock frequency - Incorrect PLL configuration - Missing or unstable or out-of-range PLL power supply

[Altera_Forum]

Ok, I'll check those.

[Altera_Forum]

It was missing PLL power supply. I will check later if PLL works correctly.