Hello everyone, long time no see =]
Recently I've built my own evaluation board with EP1C12 Cyclone device (yes, it's an old one, but I obtained it for free). The board is working, I can configure the FPGA using JTAG Byte Blaster (parallel port), also FPGA chip is working properly, except the PLL. I've created simple test project, which uses PLL. The PLL is created as a Altera Megafunction and it's suppose to double the clock frequency (from 50 MHz to 100 MHz). Reset and clock signals are connected properly to PLL core. What could be wrong ? The code is listed below.
PLL_test.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity PLL_test is
generic
(
DIV_FACTOR : positive := 20
);
port
(
clk : in std_logic;
nrst : in std_logic;
divout : out std_logic;
locked : out std_logic
);
end PLL_test;
architecture behavioral of PLL_test is
COMPONENT PLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
signal divider : std_logic_vector(15 downto 0);
signal div_rst,div_clk,PLL_lock : std_logic;
begin
clk_mul : PLL
PORT MAP
(
areset => not nrst,
inclk0 => clk,
c0 => div_clk,
locked => PLL_lock
);
div_rst <= PLL_lock and nrst;
locked <= PLL_lock;
freq_divider : process(div_clk,div_rst) is
begin
if div_rst = '0' then
divider <= (others => '0');
divout <= '0';
elsif rising_edge(div_clk) then
divider <= divider + 1;
if divider <= DIV_FACTOR/2 then
divout <= '0';
else
divout <= '1';
end if;
if divider = DIV_FACTOR then
divider <= (others => '0');
end if;
end if;
end process freq_divider;
end behavioral; The divider is supposed to generate signal with frequency ten times lower than PLL clock out frequency (10 MHz in this case), cause my oscilloscope is old and has bandwidth of 25 MHz.
