Greeting.
Using Quartus II 8.0 Web Edition, when I'm trying to set .out port of TRI buffers to some bidir pins on EPF10K10QC208-3, I get error:
Error: Node "out[48]~156" of type logic cell has no legal location
Error: Can't find fit
"out" group is defines as:
SUBDESIGN abcd
(
out[108..01] :BIDIR;
...
Assignment is done as:
for i in 0 to 12 generate
...
out[i*8+8..i*8+1] = outtri[i][].out;
...
end generate;
in Pin planner,
out[48] is assigned to PIN_119.
The project has been converted from MAX PLUS design.
At the same time, most other pins out of 108 "out" assigns without errors.
Fitter effort set to Standard Fit.
It looks strange because the assignment must not require many resources, in my view.
Can something be done with this?
