Problems writing/reading to SSRAM with Cyclone III starter board

[Altera_Forum]

Hello,  

 I have been learning to work with the Cyclone III starter board with the goal of creating a device for an undergraduate project. I have no previous experience in digital design, and only one course in C++ programming (very basic), therefore this stuff is proving to be very challenging. I have been trying to interface the Cyclone III with the SSRAM chip provided onboard the starter kit in the hopes of loading data into it from a Labview program (via SPI), with the intentions of reading it back at a later time. I have so far developed what I believed to be a functional circuit using a schematic diagram which simply set the appropriate levels for the control lines of the SSRAM while loading the target address along with the data into a shift register to be read by the A and DQ lines of the RAM. As expected this program does not work. I cannot load data into a location in memory and read it at a later time. I have not taken any timing into consideration as I have no idea where to get started on this aspect of the circuit. Could someone please offer some suggestions or guidance that may be helpful in learning enough to accomplish my goals. Thanks.  Andre

[Altera_Forum]

The most helpful advice would be simply whether or not I need to take timing into consideration for the SSRAM, and what kind of buffer to use for the bidir lines connected to the DQ lines of the SSRAM so that I can read and write. Thanks.

[Altera_Forum]

A few things I'd check. Check the SSRAM clock. It has to be 180 degrees out of phase than your data so that it can capture into the RAM. 

 For the buffer questions, my design for Cyclone II board (not Cyclone III), I use the LVTTL 3.3V. Data has to be bidirectional, the rest (adsc,bw,bwe,chipenable, outputenable and address) will be single direction from the FPGA to the SSRAM.

[Altera_Forum]

Thanks for the response. I have a few follow up questions. The input and output lines for the data are different, do I use a tri-state buffer to control whether I want to read/write the DQ lines of the RAM (which would be bidirectional). As for the phase shift between the SSRAM clock and the data my main concern is that I am not sending the data in "packets", I am more or less loading it into a shift register, then interrupting its clock, and simply reading it as static levels. Any suggestions on how to create this phase shift of 180 would be appreciated. Thanks.  

 Andre

[Altera_Forum]

Yes, you will need a tri-state buffer to do that. 

 For the clock, you can use a PLL. Instantiate it through the megawizard, under IO, you will find ALTPLL. You can have one clock to clock your shift register and the other clock phase shifted 180 degrees to clock your SSRAM clock.

[Altera_Forum]

Is there a reason that you've not considered an SOPC Builder based system with a Nios II processor? You'd get the SSRAM interface and SPI controller....for "free".

[Altera_Forum]

I highly recommend you use the SOPC builder flow. And yes, timing is very important. It doesn't matter what you design if your timing is wrong.  

 Jake

[Altera_Forum]

Well to be honest I have attempted to use the SOPC builder and it seemed as though I could not add anything without encountering errors (Error: ... must be connected to an Avalon-MM master). Do I need to download additional software for this tool? Thanks.  

 Andre

[Altera_Forum]

What you need to do is a little reading. 

 http://www.altera.com/literature/lit-sop.jsp (http://www.altera.com/literature/lit-sop.jsp) http://www.altera.com/literature/lit-nio2.jsp (http://www.altera.com/literature/lit-nio2.jsp)  You're going to save yourself a lot of time if you do the research up front.  Jake