Trying to set /change value of Input delay from pin to internal cell parameter for a clock input which is feeding to Altera GPIO Lite IP instance (set in ddr mode).However for different values of the parameter there is no change in delay across the path.Also if MAx10 allows the maximum value to be 7 then why does the quartus allows values that are greater than 7.
Kindly help
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Hello,
Also if MAx10 allows the maximum value to be 7 then why does the quartus allows values that are greater than 7.
Can you share us more details about your design regarding the problem of no change in delay across path?
Also if MAx10 allows the maximum value to be 7 then why does the quartus allows values that are greater than 7.
What is that value of 7 specifically?
Thank you!
In the datasheet under programmable IOE delay part the table specifies the max offset values that can be assigned.
In my project for a clock pin I have set the assignment as follows:
MAX24287_HMII_RXCLK Input Delay from Pin to Input Register 8 Yes ( also attached pic with the thread).
this is my latch clock for one of the timing constraint ( set input delay). Now I want to delay this clock from pin to internal register where timing has to be met, but irrespective of the value set in assignment editor, the required path timing remains same.
I tried to introduce delay by adding multiple altera gpio lite Ip instances in bypass mode, though all are synthesized, but in timing analysis only one of the instance is being considered for analysis remaining are not shown in the timing path.
Kindly help
(IF THERE IS ANY MORE SECURE WAY OF SHARING FILES ,INSTEAD OF POSTING IT IN COMMUNITY. PL LET ME KNOW.)
Hello,
Quartus does not stop you from putting the value you put even though it goes beyond the maximum. Fitter should be telling you that there is an error. You might want to check the fitter report and see if the value is corrected by itself.
Hello,
Is there any update from your end? I will close the case if you do not respond in 3 days.
Thank you.
