Programmable Master for SOPC Builder system testing.

[Altera_Forum]

Please see this link on the Nios Wiki for further information on the Programmable Master component.  

 programmable master info on nios wiki (http://nioswiki.jot.com/wikihome/programmablemaster)   overview  

• The Programmable Master is a configurable test master that allows you to create virtually any type of Avalon Memory Mapped master, pipelined, non-pipelined, bursting, non-bursting, etc. 
• The Programmable Master is delivered as an SOPC Builder component, and is intended to be integrated into SOPC Builder systems. 
• The primary use model is envisioned to be an SOPC system containing the Programmable Master which is controlled from a host workstation using the System Console infrastructure over the JTAG interface. 
• Using System Console you can write TCL scripts which load test vectors into the Programmable Master and command it to execute them, and then monitor various statistics that the master collects during execution. 
• The Programmable Master may be used in hardware deployed FPGA designs, or HDL simulation models along with the System Console infrastructure. 
• The advantage that the Programmable Master brings to system checkout and architectural verification is the simple fact that it can be configured to look like any legal master topology, and it has the ability to run test vectors at system speed. Test vectors will execute back to back as fastas the system interconnect fabric can accept them. So unlike a soft CPU or DMA controller which have predetermined constraints which they must conform to, the Programmable Master is basically unconstrained by any prerequisites, and may issue any type of data access patterns into the fabric from any type of master interface topology. 
• The Programmable Master can issue read and write transactions into the fabric. 
• Returning read data may be captured by the master, or compared against programmed vectors to detect read errors or unexpected read results. 
• Vectors may be programmed in such a way that the master executesthem one time, or loop indices may be configured to allow the master to loop thru the vectors over andover again. 
• Internal counters allow you to capture how long it takes for a sequence of vectors to execute, or count how many loops the vectors have looped thru. This allows you to derive performance metrics for how a master is actually performing in a given system environment. 
• An externally available input allows you to start and pause the master from an external signal source. This is useful for coordinating the actions of multiple Programmable Masters in a system. 
• A library of TCL scripts is provided along with the ProgrammableMaster to illustrate how one might control and interact with the component thru the System Console environment. 

[Altera_Forum]

Great!! I have not checked it yet but seems very useful.