Programming NIOS II code to EPCQ in Quartus 13.1

[Altera_Forum]

Hello  

 I'm having trouble with NIOS II code executing from an EPCQ x4 flash chip (p/n Micron N25Q256A) after a power cycle. I've followed the following guideleins to boot from EPCQ or EPCS (from Altera rd11192013_118):  http://www.altera.com.cn/support/kdb/solutions/rd11192013_118.html  I have taken the following steps (in order). According to Altera, steps 6-15 would be required *each* time I make a change to either hardware OR software and I want to program to non-volatile memory (i.e. when I do not want a JTAG cable connected to hardware). This is very time consuming. Am I missing something fundamental?   1. Added lines STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1" and ENABLE_INIT_DONE_OUTPUT ON to project qsf  2. Deleted db and incremental db in project directory  3. Pointed the reset vector of NIOS to an EPCS/EPCQ controller (connected in Qsys, with a locked base address of 0x00)  4. Pointed the exception vector to on-chip-memory  5. Generated Qsys design  6. Compiled in Quartus II  7. Converted programming file from sof to jic, specified active serial x4, added the correct p/n for the flash loader, and turned on compression (as requested by solution document)   8. Generated a jic  9. Successfully programmed and verified EPCQ  10. Power cycled - I have an LED turn on when the FPGA configures, and this LED turned on  11. Generated flash files for hardware with sof2flash --input=hw.sof --output=hw.flash -epcq --verbose  12. Generated flash file for software with elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash --verbose (this is supposed to be "epcs" even though the chip is "epcq")  13. Used nios2-configure-sof (command line programmer) to configure FPGA with hw.sof  14. programmed the device using the Nios II flash programmer using nios2-flash-programmer --epcs --base=0x00 hw.flash (the epcq needs to be programmed with the .flash file even if it had been programmed with quartus programmer earlier in .jic format)   15. nios2-flash-programmer --epcs --base=0x00 sw.flash    I have another blinking LED running in main() in my Nios C code. After running nios2-flash-programmer, the processor enters reset and the LEDs blink.   However, after a power cycle, all pins are in tri-state and neither the FPGA nor the Nios processor will configure.    Am I missing something?

[Altera_Forum]

You don't specifically say whether your hardware can successfully boot the FPGA from the EPCQ device. Can it? Forget Nios, just a simple rtl only project that, for example, flashes an LED. 

  --- Quote Start ---  ...after a power cycle, all pins are in tri-state...  --- Quote End ---   This implies the FPGA's isn't booting at all. So, I presume the only method you have of programming the FPGA is via JTAG. Is that right?  What method are you using to program the EPCQ device?  Is this custom hardware or a development kit?  Let me know and I will see if I can help.  Regards, Alex

[Altera_Forum]

--- Quote Start ---  You don't specifically say whether your hardware can successfully boot the FPGA from the EPCQ device. Can it? Forget Nios, just a simple rtl only project that, for example, flashes an LED.  This implies the FPGA's isn't booting at all. So, I presume the only method you have of programming the FPGA is via JTAG. Is that right?  What method are you using to program the EPCQ device?  Is this custom hardware or a development kit?  Let me know and I will see if I can help.  Regards, Alex  --- Quote End ---    I can successfully configure the FPGA from the EPCQ device (no NIOS processor). I simply convert the SOF output file to a JIC and program the EPCQ flash using JTAG.  The problem I am having is specifically related to NIOS. The processor will not begin executing code after configuration.  My test setup:   - After FPGA configuration, I output CONF_DONE to an LED (LED1)  - I wrote HDL to blink an LED (LED2) after the FPGA configures  - I wrote C code to blink another LED (LED3) in main()  After programming the EPCQ device, LED1 turns on and stays on, LED2 blinks and LED3 never turns on. This indicates that NIOS is not executing code, but the FPGA has been properly configured.  I used the NIOS flash loader from the NIOS command line to program the chip, in the order I gave in the original post.  I think there is a possibility that the processor is never getting reset from SRAM after configuration.  Thanks

[Altera_Forum]

Sorry Alex, I only partially answered your questions. 

 - I am converting the SOF to a JIC and using JTAG to program the EPCQ (it's a 256 Mbit Micron Serial NOR flash). - The board is an SoCKit development kit from Arrow. The FPGA P/N is a Cyclone V SoC, 5CSXFC6D6F31C8NES.  - The FPGA seems to configure, but the NIOS code never runs.

[Altera_Forum]

Are you still having problems with this? Based on what you state I'm happy the FPGA configures but Nios doesn't boot. 

 So, are you happy with the programming? I see the FPGA image can be loaded via .jic successfully. So, subsequent programming of the Nios image relies on the FPGA image booting. When programming this image, can I assume the FLASH programmer reports success?  Are you trying to run your code from the DDR3 attached to the FPGA? Can you run any code from RAM using the 'Run as Nios II Hardware' options?  Finally, we are talking about a Nios core - not the HPS avaiable in that device? Sorry to ask :) just checking...  Regards, Alex

[Altera_Forum]

You do have the 'real' licence for a nios /f core? 

Otherwise the cpu will only run while the jtag is connected.  It might also be possible to debug the epcs bootloader using the jtag debug. If nothing else it ought to be possible to use signaltap - especially if you expose the nios 'soft reset' line.  For software updates it ought to be possible to just rewrite the epcs sectors that contain the code (from code running on the nios) However the HAL functions for this are a little horrid.

[Altera_Forum]

--- Quote Start ---  You do have the 'real' licence for a nios /f core? Otherwise the cpu will only run while the jtag is connected.  It might also be possible to debug the epcs bootloader using the jtag debug. If nothing else it ought to be possible to use signaltap - especially if you expose the nios 'soft reset' line.  For software updates it ought to be possible to just rewrite the epcs sectors that contain the code (from code running on the nios) However the HAL functions for this are a little horrid.  --- Quote End ---    I'm using the /e version, which does not require a license for this (that is according to our FAE). I've been able to now program the flash device with the flash I created from the elf2flash utility after the FPGA has been configured. However, the processor stays paused. I'm thinking this may be related to stdin/stdout (I had been using JTAG UART), and this could possibly cause problems with the processor resetting.

[Altera_Forum]

Hi 

 Did you solve the problem?  In your first post you stated that the fpga image doesn't get loaded. What did you do to solve this issue?  Gruß Tobi

[Altera_Forum]

Hi, 

I have included the hex-files for FPGA configuration and Nios firmware in the jic file generation. Than the FPGA and Nios Firmware will be loaded from EPCQ256 (Micron N25Q256A). I'm using Quartus 13.1.4 build 182 and a Cyclone 5CEFA7 device.  After step 6 in the Knowledge Base Solution ID: rd11192013_118 (http://www.altera.com/support/kdb/solutions/rd11192013_118.html)  I converted the .sof and .elf files to intel hex files: First you have to generate the srec .flash files described in step 8   sof2flash --input=hw.sof --output=hw.flash --XX –verbose  Note: Replace XX with EPCS for EPCS device and replace XX with EPCQ for EPCQ device    elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose  Next convert them to ihex nios2-elf-objcopy -I srec -O ihex hw.flash hw.hex nios2-elf-objcopy -I srec -O ihex sw.flash sw.hex  Now proceed with step 7 from Solution ID: rd11192013_118 After 7f choose "Add Hex Data" to include the hw.hex and sw.hex than generate the .jic Program the EPCQ with the .jic file generated with Quartus Programmer and power-cycle the board FPGA configuration should configure and Nios firmware is starting.  Steps 8 and 9 aren't needed  Best regards Jens

[Altera_Forum]

--- Quote Start ---  Hi, I have included the hex-files for FPGA configuration and Nios firmware in the jic file generation. Than the FPGA and Nios Firmware will be loaded from EPCQ256 (Micron N25Q256A). I'm using Quartus 13.1.4 build 182 and a Cyclone 5CEFA7 device.  After step 6 in the Knowledge Base Solution ID: rd11192013_118 (http://www.altera.com/support/kdb/solutions/rd11192013_118.html)  I converted the .sof and .elf files to intel hex files: First you have to generate the srec .flash files described in step 8   sof2flash --input=hw.sof --output=hw.flash --XX –verbose  Note: Replace XX with EPCS for EPCS device and replace XX with EPCQ for EPCQ device    elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose  Next convert them to ihex nios2-elf-objcopy -I srec -O ihex hw.flash hw.hex nios2-elf-objcopy -I srec -O ihex sw.flash sw.hex  Now proceed with step 7 from Solution ID: rd11192013_118 After 7f choose "Add Hex Data" to include the hw.hex and sw.hex than generate the .jic Program the EPCQ with the .jic file generated with Quartus Programmer and power-cycle the board FPGA configuration should configure and Nios firmware is starting.  Steps 8 and 9 aren't needed  Best regards Jens  --- Quote End ---    Hi Jens,  having similar problem.. tried your instruction above with no success. could you look into my wiring digram and comment if something is missing?... This is the first time that we have use EPCQ before when we have migrated to cyclone 5. BTW the jic created from SOF with asx4 selected is the only configuration that completely configures the FPGA upon power recycling.. When I add hex data for the SW image and program, the SW doesnt execute. Only the HW image execute.. Have tried the active serial only but no success at all..   rgds, Lanz

[Altera_Forum]

Hi Lanz, 

 I have attached you a more detailed description of my configuration solution (including snippets of schematics). If your FPGA is configured after POR than the EPCQ wiring should be correct. Verify the map file generated by file convert utility, the firmware have to start immediately after FPGA configuration data.  With the attached procedure my nios system is booting correct from EPCQ.  Does anybody succeed with remote system update and EPCQ? I try the example from alterawiki (http://www.alterawiki.com/wiki/remote_update_for_cyclone_v) it works just with system console as described. I have to use Nios for the remote update because system console works just with connected JTAG cable :) I can write the application page address and initiate the reconfiguration from Nios but the application image is not loaded.  best regards Jens

[Altera_Forum]

Hi Jens, 

Thank you for your description. What the C code in your example? Where and when this is executed? My issue - if I using JIC file and configure EPCQ through the Quartus programmer, fpga is started successfully, but if I use Flash Programmer fpga fabric (not nios) has not started. I'm following the solution http://www.altera.com/support/kdb/solutions/rd11192013_118.html but not succsefull

[Altera_Forum]

Hi Jens, 

Thank you for your description. What the C code in your example? Where and when this is executed?

[Altera_Forum]

Hi Burenkov, 

 this example is belonging to a previous post from an other user (Lanz). Look at his attachment. It is a code detail from the epcs flash controller driver located in c:\altera\13.1\ip\altera\sopc_builder_ip\altera_avalon_epcs_flash_controller\HAL\src and shows which EPCQ decvice is found on my hardware during init.  Best regards Jens

[Altera_Forum]

Hi Jens, 

thanks for your answer. As I understand this solution http://www.altera.com/support/kdb/solutions/rd11192013_118.html is using JIC flash programming only for enabling 4 bytes addressing mode. So is it possible to enable 4 bytes addressing mode by the call alt_epcs_flash_init() in my nios project? I want to get configuration data via uart and write configuration flash from Nios via epsc_controller. I can not using JIC programming every time I want to update configuration. And one more question. I have some misunderstanding of nios boot in case of reset vector points on epcs controller start address. In this case some boot code must placed in flash start address, but SOF file(converted to *.flash) with configuration data placed in here. So how it is work?  Best Regards, Sergey Burenkov

[Altera_Forum]

Bootloading process is clear now) 

Enabling 4 bytes addressing mode of EPCQ256 is still in the research process

[Altera_Forum]

I have a similar setup, but I am just trying to use the NIOS to program the PROM for future RTL updates so my application is very small and fits in block RAM so no separate application image is needed. Here is what I learned: 

 

• The JIC must be set to Active Serial X1 mode. If set to X4 mode any future FPGA images converted with sof2flash will not work. The JIC will set the addressing mode and the dummy clocks which varies between X1 and X4 and breaks configuration if not set correctly. 
• If you are using a Stratix V AB device, or possibly any V series, and the Altera flash software library you must go into the code and disable the reverting to 3-byte addressing mode. I found this in the epcs_commands.c file, which appears to have been written before V series devices came out and never updated. If you don't do this you need to power cycle the system to reset the PROM's addressing mode to whatever the JIC configured. 

[Altera_Forum]

--- Quote Start ---   My issue - if I using JIC file and configure EPCQ through the Quartus programmer, fpga is started successfully, but if I use Flash Programmer fpga fabric (not nios) has not started.  I want to get configuration data via uart and write configuration flash from Nios via epsc_controller. I can not using JIC programming every time I want to update configuration.   --- Quote End ---   Hi Sergey. May I invite you to the Russian-speaking forum for discussion of this issue? I have resolved some part of problem with remote system update, but I have some more questions. Main question what is wrong with RBF-file generation? If I use RBF-file system don't start after power on. If I remove header from JIC-file and load it into EPCQ by Nios everything is OK. I use Quartus II version 14, p/n 5CEFA9.  Best Regards, Andrei.

[Altera_Forum]

Hi Andrei! 

Yes of course we can discuss it in Russian-speaking forum. I general I solved the problem for me. As you mentioned, I use JIC without header and tail. It works.

[Altera_Forum]

--- Quote Start ---  Hi Andrei! Yes of course we can discuss it in Russian-speaking forum. I general I solved the problem for me. As you mentioned, I use JIC without header and tail. It works.  --- Quote End ---   Hi Sergey. Please, read your private messages.