Stratix IV - Error 176603: cannot place node <name> at <text> because it cannot...

[Altera_Forum]

Hello all :) 

 I'm using Stratix IV (EP4SGX180KF40I3), with Quartus 11.1SP1.  I have two clock input pins: AB34 and AF6. I would like to choose between them using a CLKCTRL instance in the design (clock MUXing). I used the ALTCLKCTRL block from the MegaWizard, with the following configuration: - For Global clock - 2 clock inputs - No enable port - No "Ensure glitch-free switchover" The SELECT port for the CTRLBLK was implemented with logic (could receive both '0' and '1' values).  When I run Quartus compilation, I receive the following error messages:  Error (176603): Cannot place node CLK_125M_SEC at IOPAD_X119_Y43_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_component|sd2 placed at CLKSEL_G0  Error (176603): Cannot place node CLK_125M at IOPAD_X0_Y52_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_component|sd2 placed at CLKSEL_G4  After getting the error message, I tried also to use a constant value for the SELECT ('0'), but I received again the same error.  My questions are: - In general: Is it possible to drive these two input clock pins through a CLKCTRL block? - Do I have anything wrong in the ALTCLKCTRL block MegaWizard configuration? - Do I I have something wrong in the way I use the ALTCLKCTRL block?  Thanks, Olga

[Altera_Forum]

It appears you can't use these pins and, I think, the pin planner diagram 'shows' why. I'd suggest those two pins are too far away from each other. 

 Without the pin assignments my trial project compiles successfully. Add the two clock pins you've specified and it does not. However, removing one pin assignment (or the other) results in success.  Specifying pins AB34 & AC34 (two global clocks on pins located close together) works. Alternatively, leave AF6 in and Quartus chooses pin AC6.  So, I'd suggest the device does not have routing resource available to direct a global clock input to a clock control block located on the other side of the fabric.  Cheers, Alex

[Altera_Forum]

You're correct  

  The Explantion is found in StratixIV HandBook, Chapter 5 "Clock Networks and PLLs in Stratix IV Devices", page 5-14:   "Clock Control Block ... The mapping between the input clock pins, PLL counter outputs, and clock control block inputs is as follows: - inclk[0] and inclk[1]- can be fed by any of the four dedicated clock pins on the same side of the stratix iv device - inclk[2] - can be fed by PLL counters C0 and C2 from the two center PLLs on the same side of the Stratix IV device - inclk[3] - can be fed by PLL counters C1 and C3 from the two center PLLs on the same side of the Stratix IV device ..."