Programming S25FL256 through Cyclone 10 with file from Processor

[Jcole]

Hi,
I wanted to see if it is possible to load a S25FL256 with a Programming File (.rpd, .pof, .sof, etc) through the Cyclone 10 LP using a file received from the processor.

Essentially what I'm trying to do is update the second image seen by the remote update system, while the device is in the field and we wont have access to Quartus or JTAG. I wasn't 100% sure if there might be any built-in Intel IP that could help with this process or if the best option was to just use a Passive Serial Single-Device setup with external host (which would require a restructure of the current layout).

Thanks in advance.

[Fakhrul]

Hi Jcole,

Maybe you can start with Intel® Cyclone® 10 LP FPGA – Remote System Upgrade with System Console Design Example.

Here is the user guide for your reference: Reference guide for the design example

Regards,

Fakhrul

[Jcole]

Hi Fakhrul,

I can get the Remote Upgrade working fine, loading 2 images into the flash using Quartus and .sof files. BUT I want the 2nd image stored in flash to be a hex file that the FPGA receives via a connected processor. Is there any way to write a hex file into flash using just the FPGA and doesn't involve using a JTAG cable, Quartus, or external console?  

[FvM]

What's the relation between binary programming file in your first and hex file in your second post? Anyway you can write any data of your choice to serial flash using available IP. Transfer hex formatted programming data to FPGA is also possible, but you need to code hex to binary converter. Which interface (e.g. UART) do you want to use?

[Jcole]

I would like to have the option to rewrite the 2nd image stored in the flash that is visible to the remote update system. I can receive hex files serially or in bytes from the attached processor with no issue. When trying to explicitly use the  Altera_nCS, Altera_Data0, and Altera_dclk pins connected to the FPGA to write to the flash, I get errors in Quartus about using the pins. I figured that I would need to use a built in IP to handle this communication, but from most of the documentation on the IPs they seem to need either a JTAG connection, a console setup, or Quartus to program the flash. 

[FvM]

Hi,
accessing flash connected to AS configuration pins doesn't require specific IP, just some assignments in Quartus. Also Quartus IP like altasmi_parallel, ASMI Parallel II and Generic Serial Flash Interface IP have the option to either use internal "hidden" connection to configuration pins or to export it manually. In the latter case it's the same situation as if you are using your own flash controller.

Dual-purpose pin settings in Device and Pin Options of all connected configuration pins must be "use as regular I/O"

[Fakhrul]

Hi Jcole,

I hope the explanation above by our fellow community members, FvM would address your concern.

Regards,

Fakhrul

[Jcole]

Hi Fakhrul,

It does help, I've been trying to use the Generic Serial Flash Interface to send data. Been having some trouble with the core in simulation, I've been writing to the addresses listed in the documentation but not seeing much response out of the core. Not sure if this is a simulation issue or if all the communication will be handled behind the scenes. 

Thanks

[Fakhrul]

Hi Jcole.

Could you provide us with the simulation design?

Regards,

Fakhrul

[Jcole]

Hi Fakhrul,

I ran my design through the Cyclone 10 LP Dev Kit with EPCQ128A just to make sure the result was the same. In my design, I use a state machine to set the registers of the GSFI to conduct a WR enable, Write 1 Byte, and Rd One Byte Using the following instructions, but don't get a response from the flash:

WR Enable:
CSR_ADDR 0x7    CSR_WR_DATA  0x00000006

CSR_ADDR 0x8    CSR_WR_DATA   0x00000001

WR 1 Byte:

CSR_ADDR 0x4    CSR_WR_DATA  0x00000000

CSR_ADDR 0x0    CSR_WR_DATA  0x00000101

CSR_ADDR 0x6    CSR_WR_DATA  0x00007002

AVL_ADDR 0x004000    AVL_DATA 0xABCD1234

RD 1 BYTE

CSR_ADDR 0x4    CSR_WR_DATA  0x00000000

CSR_ADDR 0x0    CSR_WR_DATA  0x00000101

CSR_ADDR 0x5    CSR_WR_DATA  0x00000003

AVL_ADDR 0x004000   

[FvM · Accepted solution]

Hi,
signaltap waveform shows that you don't understand Avalon MM timing requirements. We see e.g. mem_read active while mem_ waitrequest is asserted which must never happen.
Imagine that mem_write starts a serial flash cycle with adress and data bits. Waitrequest indicates ongoing serial interface activity, next memory read/write can't happen before waitrequest is release. Similar problems exist with csr interface.

[Jcole]

Hi FvM,

Even after waiting for quite a while, the the mem_waitrequest is never released after the write to the data address command. Am I still using the core incorrectly?

[Fakhrul]

Hi Jcole,

I'm attempting to grasp the situation better. Could you please provide a block diagram or schematic illustrating the interconnections among the FPGA, processor, and flash?

Regards,

Fakhrul

[Fakhrul]

Hi Jcole,

I noticed that you have marked the above comment by our fellow community member, FvM, as the solution. Assuming your question has been addressed, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you on this thread. Thank you.