Programming of the CRAM of a Max10 using svf file

[acremann]

Dear all,

We try to program the configuration RAM (CRAM) of a Max10 from an svf file. This works well, but in addition, something non-volatile is altered on the Max10 as well: a previous configuration in the CFM does not load anymore after a power cycle.

The svf file is generated with

quartus_cpf -c -q 24.0MHz -g 3.3 -n p project_name.sof project_name.svf

We used openFPGALoader to program the Max10 on a DE10-Lite board.

Below I attached the svf file (as a zip file).

Thanks a lot!

Best,

Yves

[Farabi]

Hello,

Can you slow down the TCK and see if it can pass?

TCK range = 6Mhz - 24Mhz

regards,

Farabi

[acremann]

Dear Farabi

I tried that, there is no change if I set a different clock frequency (in this case 6 MHz).

I guess the code in the svf file somehow overwrites some non-volatile memory cells on the Max10.

Best,

Yves

[NurAiman_M_Intel]

Hi,

Do you get any error message?

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any further assistance needed for this case?

Regards,

Aiman

[acremann]

Dear Aiman

Thanks for your reply! There is no error message, but the issue is the following:

1.) We configure the FPGA CFM using a design, let's say "led_blinky"

2.) We power-cycle the FPGA; "led_blinky" is running (as it should)

3.) We use the .svf file (see above) to configure the CRAM of the FPGA with the design "stopwatch"

4.) We observe, that the design "stopwatch" is working as expected.

5.) Now comes the surprise: Although the design "stopwatch" was only supposed to be loaded into the CRAM (so it should not affect the design "led_blinky" in CFM), our previous design "led_blinky" is not running after power cycling the FPGA. Instead, neither of the two designs are active.

This problem is therefore not solved and unlikely related to the clock frequency.

Is there anything we can try in addition?

Thanks a lot!

Best,

Yves

[NurAiman_M_Intel]

Hi,

• Does the sof program the CRAM correctly?
• Try to get the content of CFM. Use quartus to unload the CFM and compare.

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any update for this case?

Regards,

Aiman

[acremann]

Dear Aiman

I apologize for my late answer! Yes, the CRAM is programmed correctly, the design "Stopwatch" runs when I program the CRAM from my .svf file. However, when I do a Verify of the CFM0 using the programmer after powercycling the device, the contents of the CFM0 has been altered. Verify on the programmer using the pof file from the old design now shows an error.

Best regards,

Yves

[NurAiman_M_Intel]

Hi,

What is the error shown? Can you provide the screenshot.

Regards,

Aiman

[acremann]

Hi

OK, I looked closer into the error message: After programming the CRAM using the svf file (attached below in a zip file) the CFM gets actually erased! Below the screen shot of the Programmer blank check; the CFM is empty.

So it looks like the svf file used to program the CRAM causes an erase of the CFM as a side effect.

Best,

Yves

[NurAiman_M_Intel]

Hi,

Sorry for the delay.

Per my understanding, you have two design( LED blinking and stopwatch). And after you configure stopwatch, the led blinking is not running. This is because when you configure stopwatch after LED blinking, it has overwrite the first design.

Regards,

Aiman

[acremann]

Dear Aiman

I apologize for the late reply. Yes, the issue is, that programming the CRAM with the svf file erases the CFM. This is not desired as it wears out the CFM over time. Here some background: We use MAX10 boards for teaching. Some students have a Mac. There is a solution for running the command line version of Quartus in a Docker container with Rosetta 2. This way we can generate the svf file for programming. Using OpenFPGALoader we can then program the CRAM. But this erases the CFM every time. The two designs we talked about before were just to demonstrate that the CFM gets erased.

Is there a way to fix the svf file so it does not erase the CFM, but just configures the CRAM?

Thanks a lot!

Best,

Yves

PS: Again, how we generate the svf file:

quartus_cpf -c -q 24.0MHz -g 3.3 -n p project_name.sof project_name.svf

[NurAiman_M_Intel]

• As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘ https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.