Qsys creating the wrong number of bits for some native_phy_tx buses

[Altera_Forum]

In Qsys, I have specified a straightforward TX/RX duplex transceiver with 4 channels.  

After Generate in Qsys, the block symbol shows that the serial and data I/O busses contain exactly the correct numbers of bits. However, several other I/Os have width 8, instead of 4: rx_datak, rx_disperr, rx_errdetect, rx_patterndetect, rx_runningdisp, rx_syncstatus, and tx_datak  There was an earlier version of the design that instantiated the transceiver with 8 channels, but the design has been revised thoroughly. Could there be a lingering "design state" variable that I'm unaware of?  What else might be going on?  Hopeful thanks in advance for suggestions or insight.

[Altera_Forum]

My apologies for a rookie error, now rectified. 

 I was relying on the block symbol tile in qsys, instead of copying and pasting from the _bb.v file generated by qsys. The fitter problem arose because I had specified too many unused TX outputs.