Quartus II- ALTPLL and ALTPLLCONFIG megafunctions

[AGofs]

I've generated ALTPLL and ALTPLLRECONFIG function using QuartusII,REV10.1. I'm testing them with Altera ModelSim 6.6C. ALTPLLRECONFIG is getting 50MHz (D.C=50%), ALTPLL outputs consist of C0 and C1(50MHz each). Now I'm trying to reconfigure C0,C1 outputs by changes at data_in, counter_param,Counter_type and write_param incoming signals.

Unfortunately, It doesn't work properly. I'm attaching all relevant files to this message.Where is the problem?

[Rahul_S_Intel1]

Hi , Can you please try to use this below example design. https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/quartus-ii/alt_pll_reconfig.html

[AGofs]

I've seen this example before I created my own design. The issue is another: 1). I'm changing C0 parameters by writing DATA_IN value into Counter_param( High_Counter and Low_Counter ) of C0 on the rising edge of write_param. 2). Then I'm changing C0 parameters by writing DATA_IN value into Counter_param( High_Counter and Low_Counter ) of C1 on the rising edge of write_param. 3). Then I'm making reconfiguration by rising RECONFIG for 1 clock period. All these actions I'm executing in the Test Bench. Then I'm making a simulation for some period of time and the problem begins: The parameters of C0,C1(High/Low counters) are different from the ones I wrote. Sometimes C1/High counter is different, sometimes something else is different, sometimes one of the counters is bypassed. What is a right order of the writing DATA_IN into counter_param?

[AGofs]

Hi people,

Do you have something new about this issue?

[Rahul_S_Intel1]

Can you please send me a sample design to test from myside

[AGofs]

I've attached the sample project at start of this page. You can download it.

[AGofs]

How can I attache the project once again?

[Rahul_S_Intel1]

same as like old one, before that please try the example design

[AGofs]

Hi everybody,

the attached example was built for STRATIX,not for Cycloneiii (as my attached example).

The questions are still burning:

1).Can I simulate ALTPLL and ALTPLLRECONFIG mega-functions at  Altera ModelSim 6.6C?

2). If yes,what is wrong with my TB or with my project?

3).What is a right order of writing for High_Counter,Low_counter, Odd/even, bypass etc?

[AGofs]

Good morning ,

Do you have something new about this issue?

[Rahul_S_Intel1]

Hi ,

I am kindly requesting to open a new thread for this case