I've generated ALTPLL and ALTPLLRECONFIG function using QuartusII,REV10.1. I'm testing them with Altera ModelSim 6.6C. ALTPLLRECONFIG is getting 50MHz (D.C=50%), ALTPLL outputs consist of C0 and C1(50MHz each). Now I'm trying to reconfigure C0,C1 outputs by changes at data_in, counter_param,Counter_type and write_param incoming signals.
Unfortunately, It doesn't work properly. I'm attaching all relevant files to this message.Where is the problem?
the attached example was built for STRATIX,not for Cycloneiii (as my attached example).
The questions are still burning:
1).Can I simulate ALTPLL and ALTPLLRECONFIG mega-functions at Altera ModelSim 6.6C?
2). If yes,what is wrong with my TB or with my project?
3).What is a right order of writing for High_Counter,Low_counter, Odd/even, bypass etc?