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Quartus JTAG Programming Issue

Altera_Forum
Honored Contributor II
‎05-19-2009 04:36 PM
1,227 Views

Hey guys, 

 

I'm using the Max II CPLD (64 macros). After I program (using the Byteblaster II) the chip, Quartus says it finished and verified that the CPLD was programmed. However, when I look at the signals from the chip on an oscilloscope, nothing has changed since I programmed it last (a few weeks ago). All I/O pins are assigned in my design and pin planner files. Can anyone maybe point me in the right direction? 

 

Thanks, 

Joe
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Altera_Forum
Honored Contributor II
‎05-20-2009 08:11 AM
528 Views

 

--- Quote Start ---  

Hey guys, 

 

I'm using the Max II CPLD (64 macros). After I program (using the Byteblaster II) the chip, Quartus says it finished and verified that the CPLD was programmed. However, when I look at the signals from the chip on an oscilloscope, nothing has changed since I programmed it last (a few weeks ago). All I/O pins are assigned in my design and pin planner files. Can anyone maybe point me in the right direction? 

 

Thanks, 

Joe 

--- Quote End ---  

 

 

Hi Joe, 

 

what kind of change do you expect ? 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
‎05-20-2009 02:16 PM
528 Views

Hi, 

 

The signal it was putting out was not what I had expected (and apparently Quartus as well because the simulation came out differently). So I tried loading a hopefully corrected version of the program but I got the same result. I was curious to see if it was actually programming the chip so I just set the output pins to vcc and loaded it onto the chip. The signal it put out afterwards was still the original program I had a couple of weeks ago when it should have been just high. 

 

I appreciate the help. 

 

Thanks, 

Joe
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