Quartus Pro an Lite different handling of VHDL entities problem

[Oliver_I_Sedlacek]

I've been developing a design in VHDL under Quartus 20.1 Lite and the time has come to migrate it to Quartus 23.1 Prime Pro. It's giving me a real headache because Pro is choking on stuff that compiled fine under Lite.

A typical error is:

Error(13780): VHDL error at DAC8564IFBasic.vhd(53): type of identifier "spi_master_writeonly" does not agree with its usage as "component" type

The source line is:

rsm: work.spi_master_writeonly generic map (.....) port map(....)

I still feel like quite a VHDL newbie, so I'm stumped.

[ShengN_Intel · Accepted solution]

Hi,

Have to use something like below:

rsm: entity work.spi_master_writeonly generic map (.....) port map(....)

Also can do like below as well:

use work.spi_master_writeonly;

...

rsm: spi_master_writeonly generic map (.....) port map(....)

Pro version is more strict compared to Lite version.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

[Oliver_I_Sedlacek]

Thanks for that. I don't suppose there's a document that lists these differences in strictness, as I'm seeing other problems?

Not being a VHDL guru I'm surprised that these differences are allowed in the language specification.

[ShengN_Intel]

Hi,

FYI. The synthesis engine used for both Pro and Standard/Lite version are different. Pro version uses Qsyn synthesis engine while Standard/Lite version uses Qmap synthesis engine.

May checkout this link https://www.intel.com/content/www/us/en/docs/programmable/683463/23-3/upgrade-non-compliant-design-rtl.html under section Migrating to Intel® Quartus® Prime Pro Edition for more information:

The quartus_syn synthesis enforces stricter industry-standard HDL structures. Stricter syntax/semantics check for improved compatibility with other EDA tools. The Compiler generates errors when processing non-compliant RTL.

Thanks,

Best Regards,

Sheng