Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Quartus Pro v16.1 Design Partitions Window missing 'Preservation Level' functionality

Altera_Forum
Honored Contributor II
1,825 Views

Hi 

 

I am working on a large FPGA design, and the Quartus Pro's Incremental Block-Based Compilation Feature would be very useful to me. I am currently following a tutorial on incremental block-based compilation : design partitions lecture from Altera's website (https://www.altera.com/customertraining/olt/ibbc_design_partitions_p2/presentation_html5.html) . My Quartus software (i.e. Quartus Prime Pro version 16.1) has a design partitions window but i can't find the important 'preservation level' functionality as described by the tutorial. 

 

 

Please does someone know why this is so? and where i can find this important functionality in order to perform incremental compilation on my research project? 

(i attached the Design Partitions Window) 

 

Thanks 

W
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
793 Views

I'm pretty sure that functionality was not added until 17.0. 16.1 doesn't have it. The only use for design partitions in 16.1 was for partial reconfiguration.

0 Kudos
Altera_Forum
Honored Contributor II
793 Views

 

--- Quote Start ---  

I'm pretty sure that functionality was not added until 17.0. 16.1 doesn't have it. The only use for design partitions in 16.1 was for partial reconfiguration. 

--- Quote End ---  

 

 

Thanks. I realized version 17.1 has it.
0 Kudos
Reply