Quartus failed to compile Verilog code generated by AOC compiler

[SXian3]

Environment:

Intel vLab servers quipped with Stratix-10 PAC. Software: Quartus Pro 18.1.2 with patches + acceleration stack d5005_ias_2_0_pv

I was trying to compile a simple OpenCL program into verilog using AOC, make some changes and then use Quartus to generate bitstream from it. Here is the command I used:

# generate RTL with AOC aoc -rtl gemm.cl -board=pac_s10_dc   # change to work directory cd gemm   # run the shell scripts under build folder source build/run.sh

The error message I got from Quartus when running the last command as followed. Quartus failed to open the qsys file.

Info: Performing IP Generation using the command line: /export/fpga/tools/quartus_pro/18.1.2_patches_202_203_206/quartus/sopc_builder/bin/qsys-generate {--family=Stratix 10} --part=1SX280HN2F43E2VG --block-symbol-file --quartus-pro ject=/homes/sx233/test/gemm/build/dcp --rev=afu_default --top-level-generation=true --synthesis=verilog --parallel=off kernel_system.qsys Error: Error opening /homes/sx233/test/gemm/build/kernel_system.qsys.

When I logged out and run the command again, I got a different error message:

Info: Command: quartus_sh -t add_bbb_to_pr_project.tcl Info: Using INI file /homes/sx233/test/gemm/build/quartus.ini Error (125036): Assignment value SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT for assignment OPTIMIZATION_MODE is illegal File: /homes/sx233/test/gemm/build/afu_default.qsf Line: 49 Info (125063): set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT" File: /homes/sx233/test/gemm/build/afu_default.qsf Line: 49 Info (125076): Specified assignment value "OPTIMIZATION_MODE" must include one of the following values: "Aggressive Area", "Aggressive Performance", "Aggressive Power", "Balanced", "High Performance Effort", "High Power Effort " Error (125091): Tcl error: ERROR: Illegal assignment name: IP_TOOL_VENDOR_NAME. Specify a legal assignment name. To view the list of legal assignment names, run "get_all_assignment_names".

[sstrell]

I don't know if this is the issue, but did you run the aoc command with the typo you have there? It should be "-board".

#iwork4intel

[SXian3]

Thanks for your reply.

That's a typo. I should have run the correct command, because I can see that the correct target board is used in the log from AOC.

[JohnT_Intel]

Hi,

I suspect that this might be related to the Vlab setup issue. Please create new forum case in https://communities.intel.com/groups/harp so that they can help related to Vlab related issue.

[SXian3]

Okay. Thanks John.

Actually I tried the same command on a private server, and got some similar errors... Have no idea what's going wrong.

[JohnT_Intel]

Hi,

When you mention the same error on private server, may I know the step you used and could you share with me your project so that I can duplicate the issue?

[SXian3]

I tried Quartus 17.4 and 19.1, but neither of them actually worked. In Quartus 19.1, I sourced the setup scripts to make the ENV variables are set correctly (e.g. INTELFPGAOCLSDKROOT e.t.c), and then I ran `aoc -rtl gems.cl` to generate RTL and change to the work directory. There is a XML file named `board_spec.xml` in the folder, and I just followed the commands in that XML to run the compilation.

For Quartus 17.4, it is almost the same steps, except that I have to use `aoc -c gemm.cl` to generate the RTL. I can share you with source code I have to reproduce the issue (you need to replace the TXT extension with CL). Thanks!

[JohnT_Intel]

Hi,

If you would like to genrerate C to RTL then I would recommend you to use HLS flow. Please refer to https://www.intel.com/content/www/us/en/programmable/documentation/div1537518568620.html.

The reason is that I do not think the Arria 10 PAC is able to support OpenCL to generate RTL only.