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Device: EP4CE15M9I7N
1) Bank 3 & 4 are used for DDR2 RAM. In each bank, there are two reference pin VREFB3N0 & VREFB3N1. Just confirm only one pin should be used as reference, the other one can be used as general IO, right ?
2) In the pin out list, there is dedicated pin for DDR2 DQS and CLK. Just confirm any diferential IO at banck 3 & 4 can be used for DDR2 DQS and CLK, right?
3) There are two pins for DM: DM5B0 & DM5B1. As I used 16 bit DDR2, should I assign LDM = DM5B0 or DM5B1?
4) I use high speed ADC with LVDS output based on power supply = 1.8V. But intel sepc requires FPGA LVDS IO VCCIO = 2.5V. Can connect it drectly? DC couple?
5) Configuration device EPCQ-A will replace old device EPCS16, right?
6) MSEL0, MSEL1.... requires related VCCIO = 3.3V, right? So bank 2 VCCIO = 3.3V?
7) Bead is used for separate VCC_PLL and VCCINT. How to select bead? Which impedance @ requency should be taken into account when choose bead?
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Hi,
Please find the answers inline:
1) Bank 3 & 4 are used for DDR2 RAM. In each bank, there are two
reference pin VREFB3N0 & VREFB3N1. Just confirm only one pin should be
used as reference, the other one can be used as general IO, right ?
Answer -> Yes, one pin can be used as general IO. The usage depends upon which VREF group you are using.
2) In the pin out list, there is dedicated pin for DDR2 DQS and CLK.
Just confirm any diferential IO at banck 3 & 4 can be used for DDR2 DQS
and CLK, right?
Answer -> Though the dedicated DQS pin is optional to use, please note that this pin drive the dedicated phase shift ciruitry which helps in fine tuning of the input strobe.
3) There are two pins for DM: DM5B0 & DM5B1. As I used 16 bit DDR2,
should I assign LDM = DM5B0 or DM5B1?
Answer -> Any pin can be used. Base it on the corresponding data byte placement.
4) I use high speed ADC with LVDS output based on power supply = 1.8V.
But intel sepc requires FPGA LVDS IO VCCIO = 2.5V. Can connect it
drectly? DC couple?
Answer -> Please refer to this KDB article: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd04282010_33.html
5) Configuration device EPCQ-A will replace old device EPCS16, right?
Answer -> Yes. Refer Figure 1 in the following link: https://www.intel.com/content/www/us/en/programmable/documentation/tfb1498107381358.html?wapkw=EPCS16%20migration#abq1501510072493
6) MSEL0, MSEL1.... requires related VCCIO = 3.3V, right? So bank 2
VCCIO = 3.3V?
Answer -> MSEL pins should be connected to VCCA. The value of VCCA = 2.5V.
7) Bead is used for separate VCC_PLL and VCCINT. How to select bead?
Which impedance @ requency should be taken into account when choose
bead?
Answer -> Refer Pin connection guideline, footnote 8:
(8) Use separate power island for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state
current for the supply it is connected to(VCCA or VCCD_PLL) and high impedance at 100 MHz.
What's max power current for power supply VCCINT, VCCIO, VCCA, VCC_PLL?
Can I get this value from datasheet before doing any power analysis job
for choose power supply?
Answer -> Use Early Power Estimator (EPE) tool to estimate the power. For more details and links, refer:
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1) Bank 3 & 4 are used for DDR2 RAM. In each bank, there are two
reference pin VREFB3N0 & VREFB3N1. Just confirm only one pin should be
used as reference, the other one can be used as general IO, right ?
Answer -> Yes, one pin can be used as general IO. The usage depends upon which VREF group you are using.
XSHEN -> What do mean depends on VREF group? I think you are talking about VREF is referred to its bank, right?
2) In the pin out list, there is dedicated pin for DDR2 DQS and CLK.
Just confirm any diferential IO at banck 3 & 4 can be used for DDR2 DQS
and CLK, right?
Answer -> Though the dedicated DQS pin is optional to use, please note that this pin drive the dedicated phase shift ciruitry which helps in fine tuning of the input strobe.
XSHEN -> I did not get the answer. My question is that any specified pin for DQS and CLK from FPGA side?
3) There are two pins for DM: DM5B0 & DM5B1. As I used 16 bit DDR2,
should I assign LDM = DM5B0 or DM5B1?
Answer -> Any pin can be used. Base it on the corresponding data byte placement.
XSHEN -> OK
4) I use high speed ADC with LVDS output based on power supply = 1.8V.
But intel sepc requires FPGA LVDS IO VCCIO = 2.5V. Can connect it
drectly? DC couple?
Answer -> Please refer to this KDB article: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
XSHEN -> OK, so the answer is yes.
5) Configuration device EPCQ-A will replace old device EPCS16, right?
Answer -> Yes. Refer Figure 1 in the following link: https://www.intel.com/content/www/us/en/programmable/documentation/tfb1498107381358.html?wapkw=EPCS1...
XSHEN -> OK
6) MSEL0, MSEL1.... requires related VCCIO = 3.3V, right? So bank 2
VCCIO = 3.3V?
Answer -> MSEL pins should be connected to VCCA. The value of VCCA = 2.5V.
XSHEN - > OK. Can I assign bank 6 VCCIO = 1.8V and CONF_DONE pulled up to 1.8V ?
7) Bead is used for separate VCC_PLL and VCCINT. How to select bead?
Which impedance @ requency should be taken into account when choose
bead?
Answer -> Refer Pin connection guideline, footnote 8:
(8) Use separate power island for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state
current for the supply it is connected to(VCCA or VCCD_PLL) and high impedance at 100 MHz.
XSHEN -> OK.
Can I get this value from datasheet before doing any power analysis job
for choose power supply?
Answer -> Use Early Power Estimator (EPE) tool to estimate the power. For more details and links, refer:
XQSHEN - > I know EPE tools. But the marco in excel is too old to pen. It doesn't work and will stuck computer.
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Sorry I didn't see the responses to the questions. Adding my 2nd level responses below:
1) Bank 3 & 4 are used for DDR2 RAM. In each bank, there are two
reference pin VREFB3N0 & VREFB3N1. Just confirm only one pin should be
used as reference, the other one can be used as general IO, right ?
Answer -> Yes, one pin can be used as general IO. The usage depends upon which VREF group you are using.
XSHEN -> What do mean depends on VREF group? I think you are talking about VREF is referred to its bank, right?
Answer 2 -> There are two groups of pins in each bank with a corresponding VREF. If a group is not assigned a voltage-referenced IO standard, corresponding VREF can be used as general IO.
2) In the pin out list, there is dedicated pin for DDR2 DQS and CLK.
Just confirm any diferential IO at banck 3 & 4 can be used for DDR2 DQS
and CLK, right?
Answer -> Though the dedicated DQS pin is optional to use, please note that this pin drive the dedicated phase shift ciruitry which helps in fine tuning of the input strobe.
XSHEN -> I did not get the answer. My question is that any specified pin for DQS and CLK from FPGA side?
Answer 2 -> Yes, there are dedicated CLK and DQS pins available.
3) There are two pins for DM: DM5B0 & DM5B1. As I used 16 bit DDR2,
should I assign LDM = DM5B0 or DM5B1?
Answer -> Any pin can be used. Base it on the corresponding data byte placement.
XSHEN -> OK
4) I use high speed ADC with LVDS output based on power supply = 1.8V.
But intel sepc requires FPGA LVDS IO VCCIO = 2.5V. Can connect it
drectly? DC couple?
Answer -> Please refer to this KDB article: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
XSHEN -> OK, so the answer is yes.
5) Configuration device EPCQ-A will replace old device EPCS16, right?
Answer -> Yes. Refer Figure 1 in the following link: https://www.intel.com/content/www/us/en/programmable/documentation/tfb1498107381358.html?wapkw=EPCS1...
XSHEN -> OK
6) MSEL0, MSEL1.... requires related VCCIO = 3.3V, right? So bank 2
VCCIO = 3.3V?
Answer -> MSEL pins should be connected to VCCA. The value of VCCA = 2.5V.
XSHEN - > OK. Can I assign bank 6 VCCIO = 1.8V and CONF_DONE pulled up to 1.8V ?
Answer 2 -> Yes.
7) Bead is used for separate VCC_PLL and VCCINT. How to select bead?
Which impedance @ requency should be taken into account when choose
bead?
Answer -> Refer Pin connection guideline, footnote 8:
(8) Use separate power island for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state
current for the supply it is connected to(VCCA or VCCD_PLL) and high impedance at 100 MHz.
XSHEN -> OK.
What's max power current for power supply VCCINT, VCCIO, VCCA, VCC_PLL?
Can I get this value from datasheet before doing any power analysis job
for choose power supply?
Answer -> Use Early Power Estimator (EPE) tool to estimate the power. For more details and links, refer:
XQSHEN - > I know EPE tools. But the marco in excel is too old to pen. It doesn't work and will stuck computer.
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