Questa svverification license

[JPowe1]

I installed a Questa license and I was able to load Questa and compile my design, which uses Verilog for the synthesizable part and SystemVerilog for the testbench.

When I try to simulate my design I get an error below saying Questa failed to check out a svverification license.

I looked on the SSLC website and couldn’t find a svverification license.

I have a floating standard Quartus license.

I found the link below, which refers to a Questa.lic file that’s supposed be loaded where the license path environmental variable can find it.

I attempted to create a support ticket asking how to solve this problem but I was told to post the issue on the Intel community forum.

I'm able to run the design on Vivado but there's an issue with the testbench that prevents variable data being passed through the bidirectional bus while constant values are passed through.

The design was for a homework assignment in a graduate course on verification and I haven't received permission to share it but any good reference examples of designs with bidirectional buss with UVM testbenches would be appreciated.

https://www.edaboard.com/threads/where-to-place-the-questa-lic-file-so-that-questasim6-5c-works.171271/

https://supporttickets.intel.com/_nc_external/identity/saml/SamlError

[AR_A_Intel]

Hi Sir

Welcome to INTEL forum. To further understand the issue, could you get me the:

1) Error message screen shot

2) Screenshot of Quartus II>>tools>>license setup

3) Machine OS information

4) Quartus version used

5) License.dat file

And for privacy, you can reply/attach your file in private message

[AR_A_Intel]

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you