Question about Monitor

[Altera_Forum]

Hello, 

 is it possible to synthesize the "monitors" on the altera fpgas'. There are Monitor IPs such as Avalon MM Monitor. Can I synthesize such "Monitors"?

[Altera_Forum]

Good Morning Dave, 

 Thanks!. Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].  Thanks, Aditya

[Altera_Forum]

Hi Aditya, 

  --- Quote Start ---   Is there a way to switch of the "Trimming" in Quartus. The software automatically trims all pins that does not have a fan out. Can I tell the software not to do this. I tried setting the pins to virtual pins but it did not help. [Also, I could not get all the pins listed].   --- Quote End ---  I'm not sure what you are talking about. Could you provide an example of pins that you would like to keep that are getting removed.  Perhaps the synthesis 'keep' directive is what you need?  http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vlog/vlog_file_dir_keep.htm http://quartushelp.altera.com/11.0/master.htm#mergedprojects/hdl/vhdl/vhdl_file_dir_keep.htm  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 Can I assign virtual pins to bidirectional pins. I am getting a Critical Warning "No exact pin location assignment(s) for 37 pins of 43 pins". In my .qsf file I have assigned all of these pins as virtual pins [and all these pins are Bidirectional].  Thanks and enjoy the weekend Aditya

[Altera_Forum]

--- Quote Start ---   Can I assign virtual pins to bidirectional pins.   --- Quote End ---  Why would you want to? If they are attached to physical pins, they will not get removed by synthesis.  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 How will I know if they are attached to physical pins? It is my own module. This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.   When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].

[Altera_Forum]

--- Quote Start ---   How will I know if they are attached to physical pins? It is my own module.    --- Quote End ---  Don't call them pins then. If they are the signals at the top-level of the component, they would be called ports.    --- Quote Start ---   This module is a sub-module and only the clock pins go all the way to the top. This module has some ports that connect the other modules. For some reason, the bidirectional pins get assigned to a random pins. The input pins and output pins can be declared as virtual pins, but I have problem assigning the bidirectional ones.    --- Quote End ---  Huh? This makes no sense. You cannot have only the clock pins going to the top module, and then talk about bidirectional pins getting connected. What bidirectional pins? You just stated there were only clocks!?    --- Quote Start ---    When I look at the pin planner, I don't see these pins having any particular pin location !?!! However the pin location is shown in the Fitter synthesis report. I don't know what's going on[wrong].  --- Quote End ---  The only thing that should connect to pins on the FPGA are ports on the top-level entity.  Please try to clarify what you are doing.  I know its confusing, but it helps if you are clear on what is wrong.  Cheers, Dave

[Altera_Forum]

Good Morning Dave, 

 Oops sorry! I made that mistake again [confusing pins and ports]. I have a module [Lets call it module a]. "module a" has the following pins:  a) Clock Pins [6 in number]. [I want to assign them to the ports on FPGA] b) Few Bidirectional Pins [37 in number]. c) Output pins[20 in number]. d) Input pins.[39 in number]  [I want to make b,c and d virtual]  I have assigned "a" to ports on the FPGA and in the .qsf file I have made b,c and d virtual. [Now, I expect to see "a" in the Pin Planner assigned to ports on the FPGA [I can see them]. I don't expect "b,c and d" to show up in the Pin Planner [I don't see them].  What is causing my confusion?  After compilation, the "Fitter Summary" says,  Total Pins: 43/307[14%]. [37 of them are not being assigned as Virtual Pins] Total Virtual Pins: 59.  Additional Information:  1. In the ".qsf" file, except for "a" all are virtual.  2. In the Pin Planner, I can see 6 ports corresponding to "a" ]3. When I look at the "Input Pins" in the "Resource Section" I can see 6 clock Pins and each of them are associated with a unique "Pin#" 4. When I look at the "Bidir Pins" in the "Resource Section" I can see 37 Bidirectional Pins assigned to a unique "Pin#" [eg. K10, M7]  I shouldn't be seeing the ones in Red right?

[Altera_Forum]

Hello Dave, 

 Is my problem still unclear? Should I re-frame my question?  Thanks, Aditya

[Altera_Forum]

I'm guessing bidirectional pins can't be virtual. A virtual pin routes inside the FPGA and never goes to an I/O. A bidir has a tri-state component that only exists in the I/O. I'm not sure how that would be virtual unless the tri-state was ripped out. I'm guessing the virtual assignment is ignored for those I/O.

[Altera_Forum]

So, if a module [let this be sub-module that connects other modules] has "bidirectional pins" do they automatically get a pin location on the FPGA? What if I want to use the bidirectional pins to connect other modules?

[Altera_Forum]

There are no internal tri-states. Synthesis can sometimes recode bidirectionals into muxing logic, assuming the solution is obvious. It's generally advised to avoid internal tri-states, since they don't really exist in hardware.

[Altera_Forum]

Thanks Rysc.

[Altera_Forum]

Hi Aditya, 

   --- Quote Start ---   Is my problem still unclear? Should I re-frame my question?   --- Quote End ---  Sorry for the delay in responding, I'm traveling, and only have sporadic internet access.  Its not clear to me why you want to use virtual pins. I have never found a need to use them. Its quite possible that the problems you are having are related to trying to use a feature for other than it was intended.  Rather than use bidirectional signals in components, you should use three ports; data_out, data_in, and data_oe, and then at the top-level design, use these three signals to implement a tri-state bus. Since these three signals (or ports) are unidirectional, you should be able to make them virtual.  Note, these unidirectional ports/signals can be connected to 'fake external devices' internal to the FPGA, where the fake devices can implement what you expect your external device to do. Using these fake devices, you can probably eliminate the need for virtual pins.  Cheers, Dave

[Altera_Forum]

Thanks :-)

[Altera_Forum]

I looked at my private sent message. I said Zero, but I did send you one message, So I am posting it here again since I was not sure whether you had actually received the message. 

 My message:   I used Timing Optimization Advisor[TOA] to tweak my design. The results were not consistent. [some times the teaks seems to work and some times it doesn't. Some times there are variations in the normal cases[with no tweaks] that outperforms the cases with tweaks]  Here are my observations:  observation 1:  Some of the settings after following the TOA suggestions looked like this:  restructure multiplexers: OFF state machine encoding: One Hot smart compilation: ON.   In spite of this the Fmax did not exceed one of the cases when I hadn't followed the TOA suggestions.  observation 2:  The compilation time did not change after switching the "Smart Compilation" option to ON. But in one case it reduced from 12min to 8 min.   Are these options reliable? Looks like the randomness that occurs during the compilation is very dominant. Am I doing something wrong?  Thanks, AA

[Altera_Forum]

--- Quote Start ---   I used Timing Optimization Advisor[TOA] to tweak my design. The results were not consistent. [some times the teaks seems to work and some times it doesn't. Some times there are variations in the normal cases[with no tweaks] that outperforms the cases with tweaks]   --- Quote End ---  I do not use these tools. However, a general recommendation would be to only use them when optimizing individual components, not an entire design. You may have a single poorly designed component that is affecting the entire design. Determine if all components need to run at the same clock rate, or whether the design can be arranged to have slower peripherals separated into another part of the design, and then access those components via a clock-crossing bridge.  Cheers, Dave

[Altera_Forum]

Thanks Dave.

[Altera_Forum]

Hello Dave, 

 I have a Total Negative Slack of 1646 [reduced from 17000 after adding pipeline stages in Qsys]. I have reached maximum pipeline and cannot go any further.  The Latch clock and the Launch clocks are the same. How do I solve this problem without using "set_false_path" [This basically does tells TQA not to analyse that particular path and does not solve the problem right?]   I can get rid of this error by adding "set_multicyle_path" and relaxing the timing, but is this the right way?  And also I don't get a right estimate of the Fmax unless I use the right timing exceptions right?   Addition to Above Post:  I have found that the failing path is between within the Nios and there is a huge combinational logic between the input and output.    Thanks, Aditya

[Altera_Forum]

Look at: 

http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf  You're probably well beyond what can be done in Quartus/TimeQuest. You have a design and with all the options switched it only runs so fast due to lots of logic. You may need to optimize the design. (And note that designs only run fast, so you're requirement may be too high for your design...)

[Altera_Forum]

Thanks I will take a look at it. Does this manual hold good for Qsys also?

[Altera_Forum]

Yes. (I'm not sure if it's 100% 1:1, but the principles are the same, and it shoudl be very close)