Question about input delay

[Altera_Forum]

In quartus, on assignment editor pane, what does the io feature "programmable input delay from pin to internal cells" mean? 

in the Value column, if can i enter any integer number? for example ,if i enter number 10, what does it mean? how much time does it indicate to delay? 10ps or 10ns? I don't know if i can control the delay time preciously.  thansk

[Altera_Forum]

From AN629: 

  --- Quote Start ---  To guarantee a zero hold time, the programmable input delay provides an option to add a delay to the input pin.  --- Quote End ---    The delay is either in the input path or not. So the value in the column is either 1 or 0. It is not a delay whose length is programmable.  Cheers, Alex

[Altera_Forum]

The device datasheet will have "d elay chain" section that shows the range of values you can put in and how much the delay varies, so you can control this.  

1) Note that they are not PVT calibrated, so for example, if you were able to crank up to a 1ns delay at the slow corner, it might be a 500ps delay at the fast corner. 2) If you have I/O timing constraints, the fitter will try to modify the delay chains to meet your requirements. This is the recommended way to do this. (It's also why your timing may change as you dial in constraints. For example, I've seen people only look at the slow timing model and get some "slack" on their I/O. They then modify the their I/O requirement to a value that should make the slack what they want, but after compiling, the slack isn't what they expected because the fitter chose a different delay setting. This is usually because the fitter is aware of multiple timing models and trying to meet all, but can be annoying.)

[Altera_Forum]

Refer to the Altera GPIO Delay Elements section on page 20 of the altera gpio ip core user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altera_gpio.pdf). 

 Which device family are you using? Having looked a little more thoroughly (since my previous post) it's clear Arria V, Cyclone V and Stratix V offer far greater flexibility than other families.  Cheers, Alex

[Altera_Forum]

I thought the GPIO was for Arria 10 only, but maybe it was ported back to older families. I've used assignments in the assignment editor before. Some families have multiple delay chains on the input and output path. So you might see something like D5 Delay Chain. The actual delay chains are shown in the handbook I/O section, while the values allowed and delays they incur are in the datasheet.

[Altera_Forum]

Actually, I think I'm mistaken. Some new stuff was added to GPIO for A10, but I think it worked on older families. I've always done it with assignments. (Actually, I've mainly done it with timing constraints)

[Altera_Forum]

Hi all, 

thanks for all of you. Perhaps, Alex gived out the correct hints.