Question about the PCIE descriptor format

Altera_Forum · ‎03-17-2013

Hi, I am trying to test my receiving and transmission logic which connected to the PCIE megaCore function.

Currently, I just wanna to test the functionality of my top wrapper function, so In my testbench I need to make a standard PCIE descriptor packet which is 136bits.

Below is how the receiving descriptor is decoded in the ref design:

assign is_rd = ~RxDesc_i[126] & (RxDesc_i[124:122]== 3'b000) & ~RxDesc_i[120];

assign is_wr = RxDesc_i[126] & (RxDesc_i[124:120]==5'b00000);

assign is_cpl_wd = RxDesc_i[126] & (RxDesc_i[124:120]==5'b01010);

assign is_cpl_wod = ~RxDesc_i[126] & (RxDesc_i[124:120]==5'b01010);

assign rx_dwlen = (RxDesc_i[105:96]==0)? 11'h400 : RxDesc_i[105:96];

assign rx_addr = RxDesc_i[125]? RxDesc_i[31:0] : RxDesc_i[63:32];

assign cpl_tag = RxDesc_i[47:40];

assign cpl_bytecount = RxDesc_i[75:64];

assign rdreq_tag = RxDesc_i[79:72];

assign requestor_id = RxDesc_i[95:80];

assign rx_fbe = is_cpl_wd ? 4'hf : RxDesc_i[67:64];

assign rx_lbe = is_cpl_wd ? 4'hf : RxDesc_i[71:68];

assign last_cpl = (cpl_bytecount[11:2] == rx_dwlen );

assign cpl_stat = RxDesc_i[79:77];

assign cpl_success = (cpl_stat == 3'b000);

assign bar_hit = RxDesc_i[134:128];

assign bar2_hit = RxDesc_i[130];

assign dma_tag = 8'b11111111;

assign attr = RxDesc_i[109:108];

If I only test a simple root complex initiated write function with data and the address is 32 bit, could I make my descriptor look like this:

1. [135:128] BAR hit(set to BAR0)

2. is_wr -> [126]=1, [124:120]=5'b00000;

3. rx_addr -> [125]=1, [31:0]=Nand address

I am using s2gx as my dev kit, no DMA for now. I dont think for a simple write I need to set any cpl related bits, right?

My question is: what about these bits: rx_dwlen, rdreq_tag,requestor_id,attr?

Can anyone help? Thanks

Altera_Forum · ‎03-17-2013

Please, can anyone help?