Question on LE

[Altera_Forum]

Dear all, 

 Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates?  This is happened to my designs. Im thinking how can this happened?

[Altera_Forum]

--- Quote Start ---  Hi,  can you post a small example for me ?  Kind regards  GPK  --- Quote End ---      Sure! Thanks alot!!! Im very sorry to trouble you so much. But I really need help in this.

[Altera_Forum]

The post-map netlist of your "design" clarifies, that you can implement the complete GF_mult in two Stratix LUTs (one for each bit). It also works with Cylone 4-input LUTs. I don't see a reasonable purpose of preventing this optimization in a real design.  

 If you want to cut the FPGA feature of implementing complex logic expressions in a single LUT, though. Keeping the intermediate nodes as logic cells doesn't work in a function, I fear, because functions involve a higher level of behavioural description, that abstracts from logic cells. But it should be possible by using a component instead.

[Altera_Forum]

--- Quote Start ---  The post-map netlist of your "design" clarifies, that you can implement the complete GF_mult in two Stratix LUTs (one for each bit). It also works with Cylone 4-input LUTs. I don't see a reasonable purpose of preventing this optimization in a real design.   If you want to cut the FPGA feature of implementing complex logic expressions in a single LUT, though. Keeping the intermediate nodes as logic cells doesn't work in a function, I fear, because functions involve a higher level of behavioural description, that abstracts from logic cells. But it should be possible by using a component instead.  --- Quote End ---    The reason for preventing this optimization, is that I want to see the real total number of gates utilized in the designs.   thanks for the advice. I think i should change to component instead of function

[Altera_Forum]

Your definition of "gates" is rather arbitrary, I think. Can you actually assume XOR as one "gate"? It's build of multiple low level gates internally. But FPGAs don't have the kind of gates you imagine.

[Altera_Forum]

--- Quote Start ---  The reason for preventing this optimization, is that I want to see the real total number of gates utilized in the designs.   thanks for the advice. I think i should change to component instead of function  --- Quote End ---     Hi,  if you want to stay with your old description you can use "Implement as Output of Logic Cell".  I have your design modified. You can use the Assignment Editor in order to make the assignments. You will find the editor under : Assignments -> Assignment editor. You have to set the assignment to all outputs of your gates you would like to preserve. Maybe wildcards could be used, but I'm not sure about that.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Your definition of "gates" is rather arbitrary, I think. Can you actually assume XOR as one "gate"? It's build of multiple low level gates internally. But FPGAs don't have the kind of gates you imagine.  --- Quote End ---     I get what you mean. My concern is that the my design that actually consume more XORs and ANDs end up having less number of LEs.

[Altera_Forum]

--- Quote Start ---  Hi,  if you want to stay with your old description you can use "Implement as Output of Logic Cell".  I have your design modified. You can use the Assignment Editor in order to make the assignments. You will find the editor under : Assignments -> Assignment editor. You have to set the assignment to all outputs of your gates you would like to preserve. Maybe wildcards could be used, but I'm not sure about that.  Kind regards  GPK  --- Quote End ---    Hi,  Thanks alot! But Im thinking it will be quite complicated if my design (similar pattern as the one I posted) are getting longer and complicated. Do you think is will be more wise to use components rather than functions?

[Altera_Forum]

Reviewing your posts, I didn't find any explanation, why you want to count "gates" at a medium complex level, including e.g. XOR function. I don't see a reasonable motivation, unless you are targetting to a hardware, that would actually offer this level as atomic logic element. I only found this explanation:  

  --- Quote Start ---  i think it will be odd to report a result as such in my work.  --- Quote End ---   I think, it would make more sense to count units, that are actually measuring the implementation effort for a particular design process. For FPGA, LE are clearly the correct unit, for ASIC implementation, counting AND and XOR (and some other cells) can be meaningful. But you should consider, that basic gates (AND, OR, NOT) and complex gates (e.g. XOR) have a different area requirement. To optimize a circuit for ASIC implementation, the design tool has to know the cost factors.

[Altera_Forum]

Quite honestly, I'm more inclined to believe that the OP is having a hard time understanding why her apparently more complex design with more gates results in a lesser LE usage than her apparently less complex design, than any kind of real need. 

 That's my 0.02€.