Question on LE

[Altera_Forum]

Dear all, 

 Im wondering if it is possible to have a design that actually has fewer logic gates but took up more LE than another design that has more logic gates?  This is happened to my designs. Im thinking how can this happened?

[Altera_Forum]

LEs are not logic gates, so even if the other version uses less logic gates, the design might be more complicated for LE synthesis. 

 Does the design have only logic gates?

[Altera_Forum]

yes. only using AND gates and XOR gates

[Altera_Forum]

--- Quote Start ---  yes. only using AND gates and XOR gates  --- Quote End ---     Hi,  maybe one design could be more optimize by the synthesis tool.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  maybe one design could be more optimize by the synthesis tool.  Kind regards  GPK  --- Quote End ---     in that case, can I unable the optimization in the synthesis tool ?

[Altera_Forum]

--- Quote Start ---  in that case, can I unable the optimization in the synthesis tool ?  --- Quote End ---     Hi,  why do want to disable the optimization ? How many gates do you have in your design ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  why do want to disable the optimization ? How many gates do you have in your design ?  Kind regards  GPK  --- Quote End ---     Design A has 36AND 96XOR , consumed 82 LE, while design B has 35AND 120XOR, consumed 79 LE  i think it will be odd to report a result as such in my work.

[Altera_Forum]

--- Quote Start ---  Design A has 36AND 96XOR , consumed 82 LE, while design B has 35AND 120XOR, consumed 79 LE i think it will be odd to report a result as such in my work.  --- Quote End ---    LE elements your project requires are mostly related to HOW they are connected, not only to the number of logic gates you use in the design. For example, a long AND/XOR chain could be synthesized in a few LE, if the resulting logic function can be simplified. On the other hand, if a gate output must drive a lot of input gates, the compiler may replicate it on more than one LE to meet the high fan out requirement.

[Altera_Forum]

--- Quote Start ---  Design A has 36AND 96XOR , consumed 82 LE, while design B has 35AND 120XOR, consumed 79 LE  i think it will be odd to report a result as such in my work.  --- Quote End ---    Hi,  I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT. The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).   I have a small example attached. Maybe this solves your problem.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT. The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).   I have a small example attached. Maybe this solves your problem.  Kind regards  GPK  --- Quote End ---     Hi,   I think this is very helpful. But do I change the (implement as output of logic cell) ??

[Altera_Forum]

--- Quote Start ---  Hi,   I think this is very helpful. But do I change the (implement as output of logic cell) ??  --- Quote End ---    Hi,  look into the small testcase. Open the project with Quartus. Open the assignment editor. You find the editor under : Assignments -> Assignment Editor  Kind regards  GPK

[Altera_Forum]

Using the synthesis attribute "keep" should also provide similar results. 

 That said, I hope the original poster understood what's going on here.. :)

[Altera_Forum]

--- Quote Start ---  Using the synthesis attribute "keep" should also provide similar results.  That said, I hope the original poster understood what's going on here.. :)  --- Quote End ---      how is that be done?

[Altera_Forum]

--- Quote Start ---  how is that be done?  --- Quote End ---    Hi,  rbugalho is right, you could also try to use soome synthesis attribute.  Example:  Verilog   wire net1 /* synthesis keep */;   VHDL   signal net1 : std_logic;   attribute keep: boolean;  attribute keep of net1: signal is true;   Kind regards  GPK

[Altera_Forum]

Thank you very much!!!

[Altera_Forum]

--- Quote Start ---  Hi,  I assume that your gate are all 2-input gates. In an FPGA your logic is implemented in LUT. The LUT has at least 4 input and one output. That means you can implement every logic function with 4 inputs and one output. The fitter will look for ways to fill the LUT's effectively. There is an Assignment (implement as output of logic cell) which could be used to force the Fitter to implement the outputs of the gate in one LUT (Implement as Output of Logic Cell).   I have a small example attached. Maybe this solves your problem.  Kind regards  GPK  --- Quote End ---    A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?

[Altera_Forum]

--- Quote Start ---  A simple question. In your project, you the AND gates named as and1, and2, and3, and4 and hence they can be chosen as Implement as Output of Logic Cell. But how can it be done in VHDL?  --- Quote End ---    Hi,  I'm not a real VHDL expert, but I have VHDL version of my project attached. Keep in mind that you can also use the "keep" attribute for the signals.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  I'm not a real VHDL expert, but I have VHDL version of my project attached. Keep in mind that you can also use the "keep" attribute for the signals.  Kind regards  GPK  --- Quote End ---    Hi,  ermm..where can I access the attachment?  regarding this "keep" attribute. Im still not very sure how it is done. Is is applicable to variable?   Regards, Clare

[Altera_Forum]

--- Quote Start ---  Hi,  ermm..where can I access the attachment?  regarding this "keep" attribute. Im still not very sure how it is done. Is is applicable to variable?   Regards, Clare  --- Quote End ---    Hi,  could you see the zip-file at the end of the post ?   Keep attritbute in VHDL :  signal net1 : std_logic;   attribute keep: boolean;  attribute keep of net1: signal is true;   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  could you see the zip-file at the end of the post ?   Keep attritbute in VHDL :  signal net1 : std_logic;   attribute keep: boolean;  attribute keep of net1: signal is true;   Kind regards  GPK  --- Quote End ---    ya, i saw it! thanks alot! In my design, I use functions (written as package) so all the arithmetic involved variables rather than signals. only the input and output are declared as signals.   in my case, what should I do to use this keep attribute?

[Altera_Forum]

--- Quote Start ---  Hi,  ermm..where can I access the attachment?  regarding this "keep" attribute. Im still not very sure how it is done. Is is applicable to variable?   Regards, Clare  --- Quote End ---    Hi,  can you post a small example for me ?  Kind regards  GPK