Source synchronous interface on Cyclone III without PLL

[Altera_Forum]

Hi, 

I have a source synchronous bus @ 150MHz where the clock and data lines are edge aligned. Because the data is also DDR, the original plan was to use a 90 deg. clock from the PLL to feed into the rising and falling edge I/O registers at the I/O. Now, unfortunately, all the PLLs are currently used so I'm trying to devise a way to do this without the use of the PLL.   I thought of the I/O delay chains but unfortunately they're not supported in the Cyclone family. I also thought that just physically lengthening the clock trace on the board would work but this solution also has to support clock rates down to 75MHz.  Just throwing this out here in case someone has any good ideas or has already solved a similar problem!  Thanks, Raphael

[Altera_Forum]

--- Quote Start ---  I thought of the I/O delay chains but unfortunately they're not supported in the Cyclone family.  --- Quote End ---  You can manually add logic cell delay chains to your design, keeping the logic cells by synthesis attributes. Although not that accurate, tt's cheaper than copper delay lines and also programmable.

[Altera_Forum]

Thanks for the suggestion. So you mean rather than using the megafunction (which isn't supported anyways), just add sequential elements and synthesis attributes to prevent Quartus from blowing them away and using the timing analyzer to get an estimate of the physical delay? I'm not exactly clear how this would be programmable. Could you clarify a bit more? Thanks. 

 Raphael

[Altera_Forum]

Programmable in two regards: Either by a GENERIC parameter, that defines the number of logic elements in the delay chain or actually configurable at runtime by switching the signal route through multiplexers. I'm sure you can figure it out, if it's required for your design. 

 As often mentioned in the forum, logic cell delays aren't very exact, they depend on temperature and process variations. Routing delays are added to systematic logic cell delays and add uncertainty to the delay time calculation. You can assume a delay of about 0.2 to 0.25 ns per logic cell. Quartus simulator in timing simulation mode can give you a basic estimation of the results.  How to implement logic cell delays in HDL code has been already discussed in the forum, it's also described in the Altera "Stratix Cookbook".

[Altera_Forum]

Instead of explicitly adding lcells, one may also try to specify delays in the timming constrains (set_min_delay and set_max_delay) and see if Quartus is able to produce decent results.