we use A10 GX-057 device. There is a description on UG-01143 section 3.2, page 380-381, "For betst jitter performance, Intel recommends placing the (Transceiver's) input referance clock as close as possible to the transmit PLL"
My question is, how to understand this requirement? Is it a requirement for Hardware Design (for the clock pins assignment) or for Logic Design (for the PLL clock placement when synthesizing and routing the verilog code inside FPGA)? I think it's should be the latter, but not sure.