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Question on Transceiver's Input Referance Clock should be placed close to Transmit PLL? (UG01143 - Scetion3.2)

xytech
New Contributor I
470 Views

Hi there,

we use A10 GX-057 device. There is a description on UG-01143 section 3.2, page 380-381, "For betst jitter performance, Intel recommends placing the (Transceiver's) input referance clock as close as possible to the transmit PLL"

 

My question is, how to understand this requirement? Is it a requirement for Hardware Design (for the clock pins assignment) or for Logic Design (for the PLL clock placement when synthesizing and routing the verilog code inside FPGA)? I think it's should be the latter, but not sure.

 

Thanks!

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1 Solution
Rahul_S_Intel1
Employee
77 Views
Hi, If you plan a design and it is auto route Quaruts will automatically place,If not make the constrain in Quartus qsf file. So in simple words it FPGA depend . Regards, Rs

View solution in original post

3 Replies
xytech
New Contributor I
77 Views

up

Rahul_S_Intel1
Employee
78 Views
Hi, If you plan a design and it is auto route Quaruts will automatically place,If not make the constrain in Quartus qsf file. So in simple words it FPGA depend . Regards, Rs

View solution in original post

xytech
New Contributor I
77 Views
Reply