Question with creating LED Toggle

[mHaire]

Hello,
I am learning Verilog for the first time, and following some examples in a book. I am using the Intel Cyclone 10LP Evaluation Kit. The current example is to create a design which will toggle the state of an LED on the falling edge of a switch signal.
I've written the Verilog in Quartus and I think I have my clock, and pins configured correctly. However, the state of my LED will not change and I am lost on what to do for troubleshooting.

I have tried configuring other LEDs to the flip flop outputs to debug, but they flip flop outputs do not change state. 
Could I receive some assistance on how to work through this.
I have attached my Verilog and the RTL viewer of what I have programmed.
Please let me know anything else I should attach. 

module FlipFlopToggle(
	input i_Clk,
	input switch_1,
	output led_1);
	
	reg r_led_1 	= 1'b0;
	reg r_switch_1	= 1'b0;
	
	always @(posedge i_Clk)
	begin
	r_switch_1 <= switch_1;
	
	if(switch_1 == 1'b0 && r_switch_1 == 1'b1)
	begin
	 r_led_1 <= ~r_led_1;
	 end
	end
	
	assign led_1 = r_led_1;
	
	endmodule

[sstrell]

What clock signal/pin are you using?  Have you made the pin assignments for the switch and LED correctly in the Quartus Pin Planner?

Also note that the clock enable on the output register is only going to be active for a single clock cycle and you're using an asynchronous switch input (the switch going low) to control when that enable signal is true, so there's no guarantee that the output register will be enabled to switch the LED output at the exact moment you flip the switch.  You may want to register the switch going low as well.

[RichardTanSY_Altera]

Thank you sstrell for the answer.

@mHaireDid sstrell's suggestion help in your case?

Regards,

Richard Tan

[RichardTanSY_Altera]

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