As CycloneIII devices are designed to support interface voltage levels from 1.2v to 3.3v to accommodate the need for flexible I/O interface implementation. I want to know why I can not import data form one bank which VCCIO is 2.5v and export the data to the bank which VCCIO is 3.3v ,when I complied my design in QuartusII 8.1 software, and there turned out to be some errors.
My Project Detailed description:
I used BLVDS to import serial data to serial-to-parallel converter, and then used the FIFO to store the parallel data. I want to read the data from the FIFO from another bank which is interface with a MCU. And the bank of the FPGA which interface with the MCU, its VCCIO is 3.3v.
I set VCCIO of each bank in the Pin Planner.When I complied my design with QuartusII8.1, the compilation stopped, and there there turned out to be some errors. The message console displays the errors as follows:
Error: Can't place I/O pin dataout[7] in assigned location IOBANK_2 made by User Location Constraints source.
Error: Pin dataout[7] is incompatible with I/O bank 2. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.
Is there any assignments that I made wrong? Or I can not realized my idea in this way?And how can I relaized my project ideas?
Any suggestion is greatly appreciated.
