communicatiom between external board running CDR and FPGA

[Altera_Forum]

hi all 

i need your help please.  communication between external board running CDR and FPGA I am working in connecting Startix Gx 'EP1SGX40GF1020C5' FPGA with external board .  the board Receive optical signal carrying information at 125 Mbps . and it convert this signal using CDR to tow line one for data 125 Mbps and the other for clock 125 MHZ. i need to connect the tow line data and clock to the FPGA using SMA connectors. could you please give me suggestion how can i solve this problem. which type of protocol good to use in side the FPGA . what i have to do if i want to connect directly the optical signal to the FPGA without sing the borad.  Thank you

[Altera_Forum]

Have you thought of using serdes, it contains an internal FPGA CDR circuitry. Check if it accepts your 125Mbps. If not you will need to upsample it.

[Altera_Forum]

Thank you for your reply. 

form the data Sheet the Transceivers does not support this low rate.  how can i check if serdes accept 125 Mbps and if not how can i up sample it.  Thank you

[Altera_Forum]

serdes is tranceivers, so your fpga doesn't accept that low speed. Upsampling could be more demanding than keeping your external board CDR. You need to stuff your bits externally and the receiver has to know which are the real bits from the stuffed ones. Alternatively, try your own CDR design inside FPGA(not that easy).

[Altera_Forum]

Thank you very much for your kind response.. 

 Could you please tell how can i proceed in upsampling solution. how can i stuff the bits externally and how can the receiver know which are the real bits from the stuffed ones ?   what do you mean by "Alternatively, try your own CDR design inside FPGA(not that easy)" ?  Thank you

[Altera_Forum]

There are several serial protocols or use your own, for example pass bits to 850Mbps by first passing your data(as packet + header) followed by alternating zero/ones till next packet. You will need another fpga to do that...the receiver will then detect packets from the agreed header(FSM). 

 Your own CDR: Before serdes era, we used to do that inside fpgas. There is plenty of literature, check xilinx papers. I will try to get some hopefully tomorrow.

[Altera_Forum]

hello  

 if i want to change the transmitter to transmit at data rate compatible with the SERDES like 1.25 Gbps because it 10 * 125 MHZ which is my ref clock .   what i have to do to achieve the TX 1.25 is in side Startix GX FPAG and in the other side and RX anther board with Startix GX . these tow boars connected through optical link.  ?? thanks

[Altera_Forum]

Actually, I don't see a way to use GX transceiver for lower data rates by upsampling, particularly regarding CDR operation. CDR can be imagined as a PLL locking on the serial input edges, in can't tolerate additional edges introduced by upsampling. 

 User CDR designs are mostly all digital PLL, involving oversampling of the input data stream by a sufficient factor, e.g. factor 4 as used in full speed USB. It seems still feasible for 125 Mbps in Stratix devices, particularly if DDIO or possibly SERDES circuits are utilized.  Another user CDR option is provided by PLLs with dynamic phase shifting option, as present in newer devices starting with Cyclone III, Stratix III and Arria II.

[Altera_Forum]

--- Quote Start ---  Actually, I don't see a way to use GX transceiver for lower data rates by upsampling, particularly regarding CDR operation. CDR can be imagined as a PLL locking on the serial input edges, in can't tolerate additional edges introduced by upsampling.   User CDR designs are mostly all digital PLL, involving oversampling of the input data stream by a sufficient factor, e.g. factor 4 as used in full speed USB. It seems still feasible for 125 Mbps in Stratix devices, particularly if DDIO or possibly SERDES circuits are utilized.   Another user CDR option is provided by PLLs with dynamic phase shifting option, as present in newer devices starting with Cyclone III, Stratix III and Arria II.  --- Quote End ---     Additional edge will have to be synchronised to data clk. The external upsampler will have to stuff on a faster synchronised clk.   As to serdes reference clk, that is going to be listed in serdes setup. You enter your bit rate and serilisation factor, then quartus tells you what clks can be used as reference for internal PLL of serdes.

[Altera_Forum]

could you please clarify for me more how to use SERDES ?? 

THank you

[Altera_Forum]

You go to megawizard and instantiate it(select the component from the list, possibly called altlvds). then follow the GUI. 

 this example may help(was used in stratix ii): input: video data upsampled    ENTITY serdes_rx_core IS PORT( rx_in : IN STD_LOGIC; --819.2Mbps rx_inclock : IN STD_LOGIC; -- 40.96MHz clk for pll rx_dpa_locked : OUT STD_LOGIC; rx_locked : OUT STD_LOGIC ; rx_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);-- 16:1 rx_outclock : OUT STD_LOGIC -- parallel data clk ); END serdes_rx_core;     Above serdes has internal PLL that uses 40.96MHz as reference(other figures possible), then generates 51.2MHz data clk

[Altera_Forum]

The basic point is to perform oversampling of the input data stream to recover the clock in a digital PLL. If the achievable regular design clock frequency isn't high enough, a SERDES circuit can sample the data at a multiple of the design base clock. The SERDES output has to be processed to extract the clock edges and data bits. Alternatively, DDIO cells can be used for a sampling at double design base clock.