Questions about Asynchronous RAM on CycloneII

[Altera_Forum]

I have one question regarding the asyn ram on cycloneII 

 Basically, I want to instantiate a small size of reg mem, like reg [n-1:0] mem [0:m-1], and input data into it through PIO output port from SOC(NiosII), after the data get filled into the mem, I need to synchronously output the mem data with the output clock from PLL to external device.   Not sure if this idea is workable or implementable on CyconeII?   Thanks a lot in advance.

[Altera_Forum]

What do you exactly mean with asynchronous in this case? The write logic still has to use a write enable signal. One option is to connect the we signal as write clock of a true dual port RAM. If the control signals are slow, they can be also synchronized to the design clock.

[Altera_Forum]

Thanks for your answer, 

 Got you, I have successfully get it work on the cycloneII, and the output data get verified as correct.