Questions about FPGA to ASIC

[Altera_Forum]

Hi.  

 I have a few questions about designing a ASIC that i hope some of you can shed some light on.  I currently use a 32bit ARM M3-Cortex MCU connected to a GSM-modem. I am planning to add Bluetooth and WiFi also. Lets say i wanted all this and maybe a DMA some RAM and a few ADCs in an ASIC. Pretty basic.   1. Can i get the HDL code for these components and easily add them together in an ASIC?  2. Are most of these components available in HDL for a royalty fee?  3. Is there a lot of ready made IP-Cores ready for implementation with the SOPC-builder for specifically this kind of thing?  4. Lets say the above mentioned components where to be integrated in one ASIC. What kind of size would a chip like that typically be? Using 90nm? 40nm?  5. Lets say I do the prototyping on one of the Stratix FPGA boards. What would it typically cost to make the first ASIC from a functional prototype on the FPGA board?  6. What kind of time window are we talking about from delivering the FPGA prototype to Altera until the first ASICs are available?  7. What price per chip are we talking about when mass production starts, not considering the initiation cost.  8. Any Links to examples resources and other things?  9. Any helpful hints/tips anyone?   Thanks!

[Altera_Forum]

--- Quote Start ---  Hi.   I have a few questions about designing a ASIC that i hope some of you can shed some light on.  I currently use a 32bit ARM M3-Cortex MCU connected to a GSM-modem. I am planning to add Bluetooth and WiFi also. Lets say i wanted all this and maybe a DMA some RAM and a few ADCs in an ASIC. Pretty basic.   1. Can i get the HDL code for these components and easily add them together in an ASIC?  2. Are most of these components available in HDL for a royalty fee?  3. Is there a lot of ready made IP-Cores ready for implementation with the SOPC-builder for specifically this kind of thing?  4. Lets say the above mentioned components where to be integrated in one ASIC. What kind of size would a chip like that typically be? Using 90nm? 40nm?  5. Lets say I do the prototyping on one of the Stratix FPGA boards. What would it typically cost to make the first ASIC from a functional prototype on the FPGA board?  6. What kind of time window are we talking about from delivering the FPGA prototype to Altera until the first ASICs are available?  7. What price per chip are we talking about when mass production starts, not considering the initiation cost.  8. Any Links to examples resources and other things?  9. Any helpful hints/tips anyone?   Thanks!  --- Quote End ---    Hi,  are you talking about the Hardcopy Family offered by Altera or are you talking about a  "real" ASIC ? If your design requires certain analog stuff ( e.g ADC's) I'm pretty sure that you can't get the ASIC from Altera. Have look to the Hardcopy Devices on the Altera Homepage.  Kind regards  GPK

[Altera_Forum]

I didn't realise that there was a difference. I guess all my questions above could apply to both a real ASIC and the Hardcopy family from Altera. What kind of designtools would I use to make make a "real" ASIC? What manufacturer and so on? Why should I prefere one over the other? 

 I guess I am just trying to get some hints and tips on where to start when it comes to ASIC designs. I have a good understanding of FPGA design with Altera FPGAs and want to know how to step over to ASIC design. Any suggestions are appreciated. Thanks!

[Altera_Forum]

--- Quote Start ---  I didn't realise that there was a difference. I guess all my questions above could apply to both a real ASIC and the Hardcopy family from Altera. What kind of designtools would I use to make make a "real" ASIC? What manufacturer and so on? Why should I prefere one over the other?  I guess I am just trying to get some hints and tips on where to start when it comes to ASIC designs. I have a good understanding of FPGA design with Altera FPGAs and want to know how to step over to ASIC design. Any suggestions are appreciated. Thanks!  --- Quote End ---    Hi,  there is a large difference between Hardcopy and a "real" ASIC. For Hardcopy Altera more or less replaced the programmable routing with a fixed routing. For an ASIC you need a new synthesis with a specific ASIC library which depence on the ASIC techology. For all your analog stuff you need a replacement in the choosen ASIC technology. After you have your synthesis ready you need somebody who will do the chip layout for you. You have to setup the testing for the ASIC and so on ... You see doing a real ASIC is much more complex then doing an FPGA or Hardcopy device. It is much more expensive and should be done only in case you need a lot of devices. BTW. I'm pretty sure that Altera will not offer an ASIC flow for you. You have to find a designhouse for your ASIC.  Kind regards  GPK