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Questions about Rapidio II ip core

eagles
Beginner
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Hello!
    I am trying to establish SRIO communication between Stratix 10 FPGA and Ti DSP. On the FPGA side, I used RapidIO II ip core in quartus 20.1. Now I found that the connection between them was failed.
    Below are my questions:

Q1:
    After powering on, does the FPGA and DSP automatically connect through SRIO? How do I know if the connection between FPGA and DSP is successful? Or What actions do I need to perform to make their connection successful?

Q2:
Is there an example design of S10 FPGA communicating with Ti DSP through SRIO?

Q3:
After powering on, In the RapidIO II ip core, signal port_initialized and link_initialized are always '0'. How to locate the problems? Is that a hardware connection problem?

eagles_0-1679563625067.png

 

Regards

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Kshitij_Intel
Employee
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Hi,


The RapidIO II Intel FPGA IP product and support discontinued.


For new designs, Intel recommends that you use other IPs with equivalent functions. To see a list of available IPs, refer to the Intel® FPGA IP Portfolio web page.


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
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Hi,


As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel


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