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R-Tile CXL IP Design Example simulation using Xcelium instead or VCS?

b_dub
Beginner
86 Views

From "R-Tile Intel® FPGA IP for Compute Express Link* (CXL) Design Example User Guide" ID: 723223, the simulation specifies Synopsys VCS, can Cadence Xcelium be used in place?  The IP libraries can be generated for Xcelium but can the test bench be modified to run on Xcelium as well? 

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1 Solution
JohnT_Intel
Employee
60 Views

Hi,


Currently we only support VCS simulation due to the needs of certain IP library.


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1 Reply
JohnT_Intel
Employee
61 Views

Hi,


Currently we only support VCS simulation due to the needs of certain IP library.


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