In a nutshell, RTL (Register Transfer Level) (Pre-Synthesis simulation) is the digital circuit that consists of combinational logic, memory elements, and clocks. The simulation takes place without any delays.
Eg: Consider a half adder.
module HalfAdder(
output sum,
output carry,
input input1,
input input2);
assign sum=input1^input2;
assign carry=input1&input2;
endmodule
The RTL schematic contains an XOR gate and an AND gate.
This RTL schematic is generated by simulation tool.
GATE level simulation (Post synthesis simulation): The synthesized RTL schematic is run with the provided timing delays. Gates are taken from the cell library.
Note: Sometimes, GATE level simulation results and RTL simulation results may not match. The answer is simple. If you use constructs that are not available to the synthesis tool, results vary.
