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RVALID is high after reset on Agilex 7 M-series F2H bridge

Mikhail_a
Novice
1,559 Views

Hello
I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA bus:

 

image.png

I see it even when f2h bridge is not connected to anything. Here are settings for HPS:

Mikhail_a_1-1713096235558.png

I use Quartus 23.4.

 

So probably you know what can be wrong here? 

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EBERLAZARE_I_Intel
1,486 Views

Hi,

 

Are you using this board?:

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

 

May I know how you boot up the board, using SD card etc?

Can you explain briefly how you perform the reset, is it thourgh the signal tap?

Also, if you do a power cycle of the board does the signal also behave the same?

 

If you are using the above aforementioned board, we have the GSRD for it:

https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRDDEVAGM039F

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Mikhail_a
Novice
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Hi!

You are right I use the exact same board.

I used this GSRD from the rocketboards as a reference. But as I found out its u-boot doesn't enable FPGA-HPS bridges, so I have to build u-boot as described here https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7 while using the same kernel and fsbl binary as in mentioned GSRD.

I have a custom module that holds asserted reset for couple of minutes so I have time to enable signaltap and observe its deasserting. But even without this module I see that after ninit_done is asserted i have RVALID high. I see this issue every time I boot the board. 

 

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EBERLAZARE_I_Intel
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Hi,

 

Just want to check if you are also using the latest versions of the source code releases, U-boot = socfpga_v2023.10 etc..?

 

Okay, so using the GHRD from Rocketboards, the FPGA configuration is done right before "starting the kernel", including enabling the FPGA bridges:

EBERLAZARE_I_Intel_0-1713338112384.png

 

Is it possible that you check again the signals behavior after booting to Linux as root in the signal tap? That would confirm that the bridge and FPGA enable and configured and the signal should behave as it should.

 

If you still see otherwise, let us know.

 

 

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Mikhail_a
Novice
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I use 

U-Boot SPL 2023.07-rc6 (Nov 20 2023 - 08:40:20 +0000) - got from GSRD
and  

U-Boot 2023.10-31805-g69d5338be0-dirty - built by myself according to rocketboards guide



and boot log looks like this:

 


CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM: 2 GiB
Core: 28 devices, 23 uclasses, devicetree: separate
WDT: Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
MMC: dwmmc0@ff808000: 0
Loading Environment from FAT... OK
In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net: eth0: ethernet@ff800000
Hit any key to stop autoboot: 0
10739712 bytes read in 499 ms (20.5 MiB/s)
FPGA not ready. Bridge reset aborted!
...........FPGA reconfiguration OK!
38816256 bytes read in 1817 ms (20.4 MiB/s)
32237 bytes read in 5 ms (6.1 MiB/s)
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
## Flattened Device Tree blob at 08000000
Booting using the fdt blob at 0x8000000
Working FDT set to 8000000
Loading Device Tree to 000000007eafb000, end 000000007eb05dec ... OK
Working FDT set to 7eafb000

Starting kernel ...

Deasserting all peripheral resets
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]

 

 

 

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Mikhail_a
Novice
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Some update

I've upgraded Quartus to 24.1, upgraded u-boot fsbl to 2023.10

 

and now I see that RVALID signal is low after reset, but It looks like ARLEN signal is not connected to where it should be. So on any read request the bridge returns only one transfer of data with RLAST high irrespective to any ARLEN I send. It looks like ARLEN is always zero right now.

 

Screenshot from 2024-04-17 16-34-52.png

 

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EBERLAZARE_I_Intel
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Hi,

 

I see in the old boot logs, the FPGA bridges are not setup yet:

EBERLAZARE_I_Intel_0-1713404615646.png

 

How's the latest boot log using the latest Quartus and U-boot? Is the bridge configured properly now?

 

In the new U-boot, the bridge enable is added as per line 15 & 54:
u-boot-socfpga/drivers/fpga/altera.c at socfpga_v2023.10 · altera-opensource/u-boot-socfpga · GitHub

 

Okay, for these signal is more related to the HBM2 IP and how the AXI interface is defined(HBM2 IP UG):

https://www.intel.com/content/www/us/en/docs/programmable/683189/23-4-19-6-1/axi-user-interface-signals.html

 

As I couldn't find these signals in the HPS TRM for Agilex 7, for the ARLEN it is the burst length transaction (you may find it in the above link, "axi_0_0_arlen"). How is the HBM2 IP's setting on the burst length value?

 

Anyway, I am a bit caught up on my side and the HBM2 IP is new to me too, so I may provide my responses late.

 

Thanks for your patience.

 

 

 

 

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Artavazd
Beginner
1,341 Views

Hi

 

This piece of log

FPGA not ready. Bridge reset aborted!
...........FPGA reconfiguration OK!

goes from U-Boot as it tries to disable bridges before programming FPGA, after that it enables them and as enabling bridges was successful there are no more messages about it.

 

As I see bridges are configured alright, at least I'm able to use HPS to FPGA bridge with no issues. 

 

To be honest I see no connection between HBM and FPGA2HPS bridge, they are completely separated IP and I don't think HBM can somehow help me here. 

 

I haven't seen any AXI settings for FPGA2HPS bridge such as burst length, I thought it is just supposed to support lengths more than one.

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JingyangTeh
Employee
757 Views

Hi Artavazd


I am Jingyang and I will be taking this case over from Eber.

Please give me sometime to be up to speed on this case and will reply to you as soon as possible.


Regards

Jingyang, Teh


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JingyangTeh
Employee
573 Views

Hi


For the burst length the Agilex7 support up to 16 transaction for the burst transaction as u refer below:

https://www.intel.com/content/www/us/en/docs/programmable/683567/23-1/fpga-to-hps-bridge-falconmesa-stratix-10.html


It seems like in your last reply you mentioned that you are able to communicate through the FPGA2HPS without any issues.

Are there any other issues before we close this case?


Regards

Jingyang, Teh


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Mikhail_a
Novice
544 Views

Hi

 

Unfortunately as you can see there is an AXI4 spec violation as ARLEN is not zero and the number of returned data beats corresponds to ARLEN == 0 

So I cant say the bridge works correctly

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JingyangTeh
Employee
431 Views

Hi


In the last screenshot you shared the ARLEN is 7H. Which correspond to 8 beats of data in the transaction.

Could you share any SS shot of the DATA and ARLEN where the ARLEN is 0 and there are data beats?


Regards

Jingyang, Teh


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Mikhail_a
Novice
421 Views

Hi

I'm sorry, but it seems you may have missed the fact that in all those data beats RLAST is 1 and ARLEN is 7Fh which means I should get 128 data beats for each of 16 read requests. But what you see on the picture is everything I have here, there are no more data beats.

 

Best

Mikhail

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JingyangTeh
Employee
338 Views

Hi Mikhail


Could you get another screen shot with the following signals so that we could analyze it better?


ARADDR

ARVALID

ARREADY

RDATA

RLAST

RVALID

RREADY


Regards

Jingyang, Teh


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JingyangTeh
Employee
256 Views

Hi


Any update on this case?

Are you able to get the signalTap waveform on your board?


Regards

Jingyang, Teh


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JingyangTeh
Employee
203 Views

Hi


Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.



Regards

Jingyang, Teh


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