I am using Arria 10 GX dev kit , with transceivers in my design.
I am working on 5G speed, data width is 40Bits.
so my rx_clkout should be fixed 125Mhz.
I am seeing a difference in rx_clkout, it is varying from 125Mhz-160Mhz each time when i program FPGA the clock is NOT stable,
I have given rx_clkout to SMA pin on board and checked in Picoscope.
change in clock , Is it a expected behavior?
If NO, what might be causing the issue?
This is not the expected Behavior, please check the rx_is_lockedtodata, rx_is_lockedtoref, signals.
Please go through the Intel® Arria® 10 Transceiver PHY User Guide
It has all the info you need. Please check reset sequence also. Follow Chapter 4.