Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Ram : 2 – port

Altera_Forum
Honored Contributor II
1,521 Views

 

For the Flip flop in the diagram, does it add to the latency? If the data should be available in the same clock as address to be presented, what need to be done? 

 

Thanks 

Best regards 

kenny
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
820 Views

Why do you need the data so quick? without those registers there your clock will be limited to quite a slow speed.

0 Kudos
Altera_Forum
Honored Contributor II
820 Views

When you use Megawizard there are options as to what should be registered, also the sample waveforms under Documentation will show the effect of the registers, typically each register delays the output by one cycle. If the rest of your design is pipelined, you need to see how the operation fits into the total. So if you are using pipelining to get faster clock sped in the total design you may want to register, just remember that every pipeline stage adds a clock cycle of delay so if you cannot speed up the clock enough to save a cycle, then you lose performance. For example: if you have a 5 stage pipe and you change to a 6, then if clock frequency does not increase by at least 1/5 you lose.

0 Kudos
Reply