Ram instantiation problem in post transtlation

[Altera_Forum]

hi, 

 my code instantiates 16 ROMS of 256 X 8 length each. but in post translate step, i observe in modelsim output that only 4 such ROMS are instantiated... wat may be the reason for such behaviour?   thanks, sumanth options  http://forums.xilinx.com/i/p.gif  

[Altera_Forum]

Most likely, the ROM is never read in the code, so it's removed in synthesis. You can check details in Quartus compilation reports.

[Altera_Forum]

well..... all the ROMs are read.... but in the report its giving me equivalent rom and all but one is being removed. behavioural simulation is all right. but other simulations are giving wrong results.

[Altera_Forum]

To expand on FvM comment... 

 Is there an output from your design that depends on the read from all ROMs.  If there is no logic output that depends on the read data from a ROM then the ROM will be deleted in synthesis.  The ROMS may be read by a testbench but does the result affect an output pin?

[Altera_Forum]

ya.... the next module to which the module in question is connected depends solely on the trimmed module.......

[Altera_Forum]

Do the ROMs contain the same data and are driven by the same address?

[Altera_Forum]

they contain the same data, but are driven by different addresses.....