Read-during-write "don't care" behavior for on-chip memory

[Altera_Forum]

When instantiating dual-port RAMs (M20K/M9K/MLAB etc.), Altera documentation defines three different read-during-write behaviors, "old data", "new data" and "don't care". Apparently "don't care" is what you get when inferring true dual-port RAMs using the Altera VHDL template, since whether you get the old data or new data will be undefined in simulation. (It depends on the order the simulator executes the two processes. This is also pretty bad since you easily end up with mismatches between simulation and hardware. In any case it is definitely much safer to use the altsyncram macro.) 

 What exactly does "don't care" mean in this context? For my application I don't care whether I get the new or old value when reading and writing to the same address in the same clock cycle, but anything else could have bad consequences.  - Is there any chance I could get a mix of the old and new value? (i.e., garbage?) - Is there any chance I could get a meta-stable output?  While I have a single-clock true dual-port RAM in M20K (I need one write port and two read ports), the question apparently applies to all RAM configurations, including dual-clock RAMs and even single-port RAMs. (The Arria 10 handbook says under the "don't care" mode that "For M20K memory, the Quartus Prime software does not analyze the timing between write and read operations.")

[Altera_Forum]

--- Quote Start ---  When instantiating dual-port RAMs (e.g., M20K/M9K/MLAB), Altera documentation defines three different read-during-write behaviors, "old data", "new data" and "don't care". Apparently "don't care" is what you get when inferring true dual-port RAMs using the Altera VHDL template, since whether you get the old data or new data will be undefined in simulation. (It depends on the order the simulator executes the two processes. This is also pretty bad since you easily end up with mismatches between simulation and hardware. In any case it is definitely much safer to use the altsyncram macro.)  What exactly does "don't care" mean in this context? For my application I don't care whether I get the new or old value when reading and writing to the same address in the same clock cycle, but anything else could have bad consequences.  - Is there any chance I could get a mix of the old and new value? (i.e., garbage?) - Is there any chance I could get a meta-stable output?  While I have a single-clock true dual-port RAM in M20K (I need one write port and two read ports), the question apparently applies to all RAM configurations, including dual-clock RAMs and even single-port RAMs. (The Arria 10 handbook says under the "don't care" mode that "For M20K memory, the Quartus Prime software does notanalyze the timing between write and read operations.")  --- Quote End ---    My guess is that "don't care" option is useful in case your design actually avoids read during write. You shouldn't otherwise use it but select old data or new data as available.

[Altera_Forum]

In the real chip, The only 2 options are old data and new data. If new data is chosen, then extra logic is required to pass the new value through to the read port. 

The whole point of dont care is you let the synth tool decide which version of ram to build.  Which template are you referring to? In VHDL simulation you can guarantee old data or new data for the read value by either using a signal as the ram storage (old data) or a shared variable (new data). You cannot get an X. X would only be possible if you added extra code to explicitly return X (because otherwise you get a multiple driver situation). The altsyncram will have this in it.  So, I think you need to be a little clearer about exactly what you're using. The whole point of return 'X' is for people who do care - to ensure they never read and write to te same port on the same clock cycle.

[Altera_Forum]

--- Quote Start ---  In the real chip, The only 2 options are old data and new data. If new data is chosen, then extra logic is required to pass the new value through to the read port. The whole point of dont care is you let the synth tool decide which version of ram to build.   --- Quote End ---    I think you are not right Tricky. Here is a cut from an Altera internal memory doc:  The same-port RDW occurs when the input and output of the same port access thesame address location with the same clock. The same-port RDW has the following output choices: ■ New Data—New data is available on the rising edge of the same clock cycle onwhich it was written. ■ Old Data—The RAM outputs reflect the old data at that address before the writeoperation proceeds.1 Old Data is not supported for M10K and M20K memory blocks insingle-port RAM and true dual-port RAM. ■ Don't Care—The RAM outputs “don't care” values for the RDW operation

[Altera_Forum]

--- Quote Start ---  Which template are you referring to? In VHDL simulation you can guarantee old data or new data for the read value by either using a signal as the ram storage (old data) or a shared variable (new data). You cannot get an X. X would only be possible if you added extra code to explicitly return X (because otherwise you get a multiple driver situation). The altsyncram will have this in it.  --- Quote End ---    Open a file in Quartus and go to Edit -> Insert Template -> VHDL -> Full Designs -> True Dual-Port RAM (single clock). Have a look at the comment in the top of the template. Funny enough, this template will give you "new data" behavior for write A/read B and "old data" for write B/read A. At least with my simulator, with a different simulator executing the processes in the opposite order you will get the opposite. The hardware will be "don't care", whatever that means.  I have always assumed that you either got "old data" or "new data", but now I don't know what to believe.

[Altera_Forum]

For Cyclone IV (M9K), it is stated quite clearly in the documentation (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51003.pdf) that don't care means either old value or new value, and not a combination of both or a metastable signal: 

 "For mixed-port read-during-write operation with dual clocks, the relationship between the clocks determines the output behavior of the memory. If you use the same clock for the two clocks, the output is the old data from the address location. However, if you use different clocks, the output is unknown during the mixed-port read-during-write operation. This unknown value may be the old or new data at the address location, depending on whether the read happens before or after the write."  The Xilinx 7 series memory user guide (http://www.xilinx.com/support/documentation/user_guides/ug473_7series_memory_resources.pdf) appearently states that for dual-clock memories, RDW is never safe regardless of the mode, and for single-clock, RDW is safe if the write port is in READ_FIRST ("old data") mode, but not in WRITE_FIRST ("new data") mode.  I'm starting to think that it would be a good rule to always avoid read during write unless absolutely necessary.