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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Readout configuration CRC after configuration

Altera_Forum
Honored Contributor II
‎11-21-2011 04:56 PM
1,051 Views

Hi, 

 

I'm trying to setup a mechanism to verify that a configured FPGA is configured with the code that the software expect. 

 

Currently, during build I insert the SubVersion revision number into the FPGA design. This number can be read by the software. 

Works but has some problems. The SubVersion revision number can change without changing the FPGA source. 

 

Next idea. 

If I could read back a CRC of the configuration bitstream after configuration, I could compare the CRC reported from FPGA with a CRC generated from the building process of the FPGA binary. 

 

I have found that there is a cycloneiii_crcblock component that might do this but I can not get it to build nor simulate. 

 

Has anybody used the crcblock i CycloneIII or has any other solution to my problem ? 

 

Thank's 

 

/Henrik
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