Real worth & Simulation has big mismatch.

[Altera_Forum]

Hey again kind folks of Alteraland, 

 The design I'm working on has a timing simulation delay of 10ns. However, when it's implemented, the pins of the FPGA is producing an output that has a delay of 6 microseconds. What is a good process of debugging this problem? I have no experience of debugging this problem as I can't hook up a probe in the FPGA chip.  Thanks

[Altera_Forum]

There is no hardware in a FPGA, that could produce a microsecond range delay on its own, except for a huge capacitive pin load, or a moderate load with an open drain output. You may want to describe your test setup more detailed.