Realization MFM de/en-Coder via MAXII

[Altera_Forum]

Hello @ All, 

I'm new here and I hope that someone can help me concerning matter above.  Background: I work almost honorary in my spare time for the computer museum in Munich and my goal is to transfer vintage Computer/Storage to new technology like FPGA and ARM-7 MCU.  For more details, I want to refer to my homepage .  Right now, I have a big hurdle:confused:: Realizing mfm encoders and decodersin the FPGA/MAXII. I haven't found the right references until now. I am working here with a magnetic device with all the preemphasis stuff and phase shifting around and this is really a piece of complicated hardware ( for me ). To rebuild this piece of hardware in FPGA related to the RLV-12 engineering drawings, it is still not clear to me how to realize the 5nsec delay logic in the FPGA and furthermore I don't know the ROM code for the phase-moving logic to get it in the FPGA. It is also not clear yet whether I need this all.  My question:

1. Has someone references how to get implemented a MFM de/en-Coder logic in FPGA? 
2. How can I realize a 9x 50nsec delay in FPGA? 
3. How can I implement a ROM , 32x8bit in FPGA?

My environment:  Quartus II 9.1 Web Edition Software  MAXII-Micro-kit-Board  ( more details on my homepage , chapter 1.4 )      Best regards from Germany/Munich and many thanks in advance,      Reinhard

[Altera_Forum]

Reinhard,  

 just had a look at your web page, good old days :-) i personaly started with a PET 2001 i guess it was 1979 ...  first MaxII is a CPLD not a FPGA  i could give you some help, prefered in our native laguage :-) via PM   Do you have more information about the MFM ? a single ton or multiple tones at the same time ?   implementing ram rom is easy, depending upon the HDL language you use.  Grüße aus der Südpfalz  Michael

[Altera_Forum]

Hallo Michael, 

I will send you a PM and many thanks for the offered help. Reinhard P.S. Can't reach you via PM/E-Mail, sorry  Anyway, the MFM ( Magnetic Recording system with Peak shift compensation) architecture ist based on US Patent Nr. 4,553,178. I can't include a link here, but on my hompage , chapter 1.2 is a link included to the engineering drawing. On page 23 , You will find the MFM ENCODER and on page 24 the MFM DECODER.. The challenge is to rebuild this part of the circuit diagram in MAXII architecture.

[Altera_Forum]

Sorry Reinhard, 

 PM was closed but should be open now ... give it a try, it works some else mailed me ...  had a quick look at page 23 the lower part seems pretty straight foreward  a shift register which taps are the adr of that prom.  the upper part is good old fashioned "digital" logic :-) the 50ns delay with taps each 5 nsec is some kind of shift register with a 5nsec clock what means 200MHz and that is fast ... if a MaxII can handle that ... were is the datasheet ..

[Altera_Forum]

--- Quote Start ---  MaxII is a CPLD not a FPGA  --- Quote End ---   By it's technology, MAX II is a simple FPGA with built-in configuration flash. The logic elements are SRAM based in contrast to a EEPROM based CPLD cells. You'll also notice, that MAX II uses the Quartus FPGA related tools, while MAX 3000 and 700 are using a different compiler/fitter.  But anyway, it's capable of performing at 200 MHz clock frequency. As a disadvantage, it hasn't any PLL or clock multiplier, so you must supply a 200 MHz clock input (or at least 100 MHz when using both edges). A full featered FPGA with PLL could use a convenient 10 or 20 MHz clock.  MAX II has no internal RAM or ROM, but 32x8 can be made in MAX II logic cells.

[Altera_Forum]

Hello and many thank for the upgrade infos 

@ MSchmitt : I have no datasheet, only the old engineering drawings and I only know the logic was based on 74S... chips, 0.4ns. @ FvM : No good news for me. I am using the MAXII-MICRO.Kit-Board  because in my opinion it should be easy for use for beginners ( included USB blaster), but runs only at 50MHz and I see no change for upgrading to 200MHz. ( soldering ?) At least, I also have to implement a 10240 byte track-holding-FIFO ... and MAXII has no internal RAM?  Do you have any recommendations which development board would fulfilling this request ? Regards, Reinhard

[Altera_Forum]

Well if MaxII runs @ 200MHz what i haven't tried yet there are some other points to consider. if the design runs with 200MHz and 8.2MHz then some kind of clock crossing must be taken into account. but it is also possible to run the design at 200MHz and have some kind of clock enable that has 1 200MHz clock pulse every 8.2MHz (too keep the design fully synchronous)  

another question what needs to be implemented inside the fpga except page 23 ?  you talked about 10240 byte fifo that could be implemented with 20 M4K memory blocks cyclone II fpga offers.   as you are new to the quartus world and fpga as well, did you had a look at the schematic entry possabilities quartus offers ? if you look at your page 23 there are some 7474 at the bottom, you can also draw such a logic with quartus. this tool is capable to handle hdl and schematic entry in a mixed combination.   i had converted a couple of old schematics (like some arcade classics) into pure verilog designs and sometimes the asyncron design to fully synchrnous conversion was a heavy task, but what worries me in your design are the two signal delay lines one 50ns with a tap each 5ns and the other one i have seen with 100ns delay and a tap each 10ns. they can be seen as shift registers with a high clock rate.  so what amount of logic do you want to transfer to a fpga and what kind of help could be give to you ?

[Altera_Forum]

Reinhard, 

 just to give you an example how the conversion from your schematic to verilog could look like here are some few code snippets ...   --- Quote Start ---    --- Quote End ---   Lets starts with the toggle DFF from the lower left corner  --- Quote Start ---  reg E128; always @ ( posedge Clk_8_2Mhz )  E128 <= ~E128;   wire RLVA_SYS_1H; wire RLVA_SYS_0H; assign RLVA_SYS_1H = E128; assign RLVA_SYS_0H = ~E128;   --- Quote End ---    now the shift register E117   --- Quote Start ---  // The shift register from Page 23 at the bottom; reg [4:0] E117; always @ ( posedge Clk_8_2Mhz or negedge RLV9_INIT_0L )  if ( !RLV9_INIT_0L )  E117 <= 4'd0;  else  E117[4:0] <= { E117[3:0] , RLV_MUX_DATA_H };  --- Quote End ---   now the ROM E120 82S123  implemented as priority encoded wires .... well at 8.2MHz i don't worry about timing here this could also be implemented as a memory and initialised from a file but strictly implemented from original schematic without 1 clock delay a register would give it is done this way ... without propper values   --- Quote Start ---  wire [4:0] PROM_E120; assign PROM_E120 = ( E117 === 5'H00 ) ? 5'b00000 :  ( E117 === 5'H01 ) ? 5'b00000 :  ( E117 === 5'H02 ) ? 5'b00000 :  ( E117 === 5'H03 ) ? 5'b00000 :  ( E117 === 5'H04 ) ? 5'b00000 :  ( E117 === 5'H05 ) ? 5'b00000 :  ( E117 === 5'H06 ) ? 5'b00000 :  ( E117 === 5'H07 ) ? 5'b00000 :  ( E117 === 5'H08 ) ? 5'b00000 :  ( E117 === 5'H09 ) ? 5'b00000 :  ( E117 === 5'H0A ) ? 5'b00000 :  ( E117 === 5'H0B ) ? 5'b00000 :  ( E117 === 5'H0C ) ? 5'b00000 :  ( E117 === 5'H0D ) ? 5'b00000 :  ( E117 === 5'H0E ) ? 5'b00000 :  ( E117 === 5'H0F ) ? 5'b00000 :  ( E117 === 5'H10 ) ? 5'b00000 :  ( E117 === 5'H11 ) ? 5'b00000 :  ( E117 === 5'H12 ) ? 5'b00000 :  ( E117 === 5'H13 ) ? 5'b00000 :  ( E117 === 5'H14 ) ? 5'b00000 :  ( E117 === 5'H15 ) ? 5'b00000 :  ( E117 === 5'H16 ) ? 5'b00000 :  ( E117 === 5'H17 ) ? 5'b00000 :  ( E117 === 5'H18 ) ? 5'b00000 :  ( E117 === 5'H19 ) ? 5'b00000 :  ( E117 === 5'H1A ) ? 5'b00000 :  ( E117 === 5'H1B ) ? 5'b00000 :  ( E117 === 5'H1C ) ? 5'b00000 :  ( E117 === 5'H1D ) ? 5'b00000 :  ( E117 === 5'H1E ) ? 5'b00000 :  5'b00000 ; // now we assign the output bits of the PROM the names as used by the schematics wire RLVA_B0_H; wire RLVA_B1_H; wire RLVA_B2_H; wire RLVA_B3_H; wire RLVA_B4_H; assign RLVA_B0_H = PROM_E120[0]; assign RLVA_B1_H = PROM_E120[1]; assign RLVA_B2_H = PROM_E120[2]; assign RLVA_B3_H = PROM_E120[3]; assign RLVA_B4_H = PROM_E120[4];  --- Quote End ---    last but not least the counter at the lower right   --- Quote Start ---  reg [3:0] E125; always @ ( posedge Clk_8_2Mhz or negedge RLV9_INIT_0L )  if ( !RLV9_INIT_0L )  // async nCLR  E125 <= 4'd0;  else  if ( RLVA_SYS_0H ^ RLVA_R0_H )  // nLOAD  E125 <= { RLVA_B4_H , RLVA_B3_H , RLVA_B2_H , RLVA_B0_H };  else  // normal count operation  E125 <= E125 + 4'd1;   // again assign output bits the name of used by schematics wire RLVA_R0_H; wire RLVA_R1_H; wire RLVA_R2_H; wire RLVA_R3_H; assign RLVA_R0_H = E125[0]; assign RLVA_R1_H = E125[1]; assign RLVA_R2_H = E125[2]; assign RLVA_R3_H = E125[3];  --- Quote End ---  

[Altera_Forum]

Hello Reinhard, 

 Need for FIFO memory is a sufficient reason to use a full featured FPGA for the design. I would recommend Cyclone III, Terasic DE0 is a possible hardware platform.

[Altera_Forum]

Hello, 

many many thanks for all your effort and information you provided ! Based on your good explanations and examples, I think , this is feasible for me. Concering the other issues, I have no plan yet. Speed up the MAXII or use another FPGA development board. Best regards, Reinhard

[Altera_Forum]

Reinhard, 

 as FvM already said i would also go for a FPGA like Cyclone III instead of a MaxII. Cyclone FPGA have some PLLs you can use to create required clocks out of other clocks. the created clocks can be faster and / or slower than the input clock. also they offer on chip memories you can use for the fifos and these memories run as fast as the fmax of the design can be in that FPGA. also you have enough resources for clock crossing and other stuff. the designs i had done with cyclone II and cyclone III (same sources) were faster compiled for the cyclone III target and had higher fmax. also the cyclone II has only the EP2C20Q240 as a device that is "hand solderable" and the cyclone III family offers a bigger range of devices were you can starte with a smal device and if needed and you have obeyed the migration rules, replace by a bigger device. the smalest "hand solderable" footprint is a TQFP144 if you would go for your own target pcb. there are some dev kits out there like the bemicro or the ebv dev kit that have usb blaster like jtag support on board and some user io pins. both with a cyclone III fpga. do you know how many IOs you will need ?

[Altera_Forum]

Hallo Michael, 

also to you, many thanks for the upgrade infos which I have to sort now. Anyway, it looks like to make a switch over to cyclone III fpga? Chapter 1.4 on my home page provides a block diagram and I need about 32 IO's .  I still can't send any PM's because I have not the requested post count reached yet, but if you prefere direct contact, you will also find my contact data on my hompage.

[Altera_Forum]

Hello again with one open key-issue: 

For the MFM Decoder/Encoder, I need a 8.2MHz clock. The half frequency 4.1MHz is available via I/O connecter distributed from the controller. Basically, I have to double phase-synchronize the 4.1MHz clock. The answer is a PLL, but the altpll megafunction is not supported by the selected device family MAXII. Realy bad for me. Is there a alternative suggestion available ?

[Altera_Forum]

A double frequency clock can be generated by a delay (either RC circuit or a logic cell chain) and a XOR gate. 

Some references for logic cell delay, also discussing the limitations.  http://www.alteraforum.com/forum/showthread.php?t=2418 http://www.alteraforum.com/forum/showthread.php?t=3068

[Altera_Forum]

Hello, 

many thanks for the upgrade infos. The notes concerning double frequency clock were not very helpful to me, but I know that the problem lies in my person because I don't understand VHDL very well and the MAXII was not the right decision for my project. Anyway, I was able to design a double frequency circuit based on my "old" digital-logic-knowledge as you can see in the appendix. It's basically a simplified PLL without VCO , but works fine and may be helpful for other people? I still have a small problem now: Generate a sector pulse like here: ____-----------_______________________________-----------_____ ----|>62.5 us<| ----|> ------------------- 625 us ---------------->|  Sight from my "old" person , I would be able to fix this problem with 2 external NE555 timer chip ( within 2 hour soldering ) but this is not the manner like it should be. Has somebody an idea to realize this timing ? Many thanks and best regards, Reinhard

[Altera_Forum]

62,5uSec = 16kHz clock 

the period is 10 times the clock  so you need a clock or an clock enable that is 1 every 62,5uSec  verilog HDL  reg [3:0] counter; always @ ( posedge my16khzclock ) if ( counter === 4'd0 )  counter == 4'd9; // this reload the counter else  counter <= counter - d'd1;  now you have a counter that counts down from 9 to 0 and then reloads to 9 again. that is your period of 625uSec, assuming you have a correct clock.  now the output signal, that could be a register or combinatorical  wire mypulse; assign mypulse = !counter;  or  reg mypulse; always @ ( posedge my16khzclock ) if ( counter === 4'd0 )  mypulse <= 1'b1; else  mypulse <= 1'b0;  now mypulse should be 1 for a single my16khzclock cycle every 10 cycles.

[Altera_Forum]

Since I am not so good in VHDL , I would prefere a wiring diagram if possible. For me it is not clear how a 16kHz clock can generated based on the only 50 MHz clock available on MAXII.

[Altera_Forum]

hmmm 16kHz is 50MHz div by 833.333 and i guess you need it accurate ... 

give me a minute or two ...

[Altera_Forum]

have a look into the zip, it contains a verilog source and the schematic symbol for it. 

place both files into your project directory now you will find a new symbol you can add to your schematic entry. add the 50MHz clock input and you should get the pulse at the output

[Altera_Forum]

many many thanks for your efforts! 

That's brilliant ! Conclusion for me: I have to learn VHDL... Regards, Reinhard

[Altera_Forum]

oooops .. i shouldn't code something while having lunch ... 

 please replace the file, it works now.